Abstract: Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter.

Abstract: Improved apparatus, systems and methods, such as those for testing an error correction code (ECC) encoder/decoder for solid-state memory devices, are provided. In one or more embodiments, the improved systems and methods deliberately inject errors into memory storage areas of memory devices to test the operation of the ECC encoder/decoder.

Abstract: A process for depositing titanium silicide films via chemical vapor deposition takes place in a deposition chamber that has been evacuated to less than atmospheric pressure and utilizes, as reactants, the organometallic compound tertiary-butyltris-dimethylamido-titanium and a silicon-containing compound such as silane. The deposition temperature, which is dependent on the nitrogen source, is within a range of 400 to 800° C. The low end of the temperature range utilizes a plasma-enhanced deposition process, while the higher end of the temperature range relies on thermal decomposition to initiate the reaction. The films deposited using the process have a sheet resistance of about 2 to 10 ohms per square and contain less than 5 percent carbon impurities and less than 5 percent oxygen impurities by weight.

Abstract: A layer of polyimide or polysilicon is used as a mask in vapor hydrogen fluoride etching. Both non-photosensitive and photosensitive type polyimide may be use. A non-photosensitive polyimide mask requires the use of photoresist for patterning with a lithographic mask. Alternatively, photosensitive type polyimide may be patterned directly with the use of a lithographic mask. The resulting polyimide mask enables the etching of very small features with great uniformity. Such etching may be used to expose micropoint emitters of field emission devices.

Abstract: A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal is comprised of a logic circuit for receiving first and second signals produced by the locked loop. The logic circuit determines if a predetermined phase relationship exists between the first and second signals and produces an output signal indicative of that determination.