Abstract: A state machine in a computer system receives operation parameters, a clock signal and control signals from a control device. The state machine provides output signals in logical output states to perform an operation based on the operation parameters, the clock signal and the control signals. The operation parameters provided by the control device include timing parameters and state parameters which are stored. A counter provides a counter output based on the clock signal and based on the stored timing parameters. A counter control circuit compares the counter output with timing parameters and controls operation of the counter based on the control signals provided by the control device and based on the comparison of the counter output with the timing parameters. A state generator compares the counter output with the state parameters and generates the output signals in logical output states, each logical output state having a duration based on the comparison of the counter output with the state parameters.

Abstract: A finite state machine has outputs variable between a finite number of logical outputs states. A clock provides a clock signal having clock pulses, with a frequency, to the state machine. A functional circuit determines the logical output states of the state machine based on state inputs to the functional circuit. A variable timer is coupled to the clock and the functional circuit. The variable timer controls the duration of each logical output state to adjust for changes in the clock frequency based on timing parameters provided to the variable timer. The variable timer varies a number of clock pulses corresponding to each logical output state so the duration of each logical output state remains within a predetermined time limit.

Abstract: A microprocessor access arbitration network which arbitrates among HOLD, RESET and REFRESH request commands by controlling a preempt bus so that a system memory refresh cycle is never delayed by a DMA or bus master operation is described. If a HOLD request is in progress for an operation other than a REFRESH cycle when a REFRESH cycle is initiated, that HOLD request is delayed while the REFRESH cycle proceeds to completion.

Abstract: A controller for interfacing bus-coupled peripheral devices with a microcomputer is described. The controller provides generalized compensation for variations in peripheral device access recovery time and for differences in access recovery times among peripheral devices, central processing units and input/output buses.

Abstract: A synchronous bus controller which provides a functional control link between one or more microprocessors and an asychronous main input/output bus is provided. The bus controller includes a state machine and data bus width determining logic enabling the bus controller to initiate and control access operations between microprocessors and accessible devices on the main input/output bus when the microprocessor and the accessed device may have different data bus widths. The bus controller includes logic circuitry to determine the number of access cycles required to complete a requested access operation and detects the last access cycle of a current access operation to terminate an access operation and provide a ready signal to the microprocessor indicating that the bus controller is ready for the next access request.

Abstract: An asynchronous memory control Unit for asynchronously controlling access to and from system memory of a microcomputer system in response to control signals from conventional and state-of-the-art microcomputer I/O buses is described. The asynchronous memory control unit of the present invention operates cooperatively with a synchronous memory control unit which provides access to and from system memory in response to command signals from a microprocessor. Whenever the microprocessor controls the bus, the synchronous memory control unit is enabled; whenever the microprocessor is not controlled of the bus at main IO bus, the asynchronous control unit is enabled.

Abstract: A direct memory access controller for computer systems in which the data may be manipulated and acted upon during a transfer to and from locations in memory, or from locations in memory to and from input/output devices. For computer systems having data word widths of two or more bytes of data fewer bus cycles are required for data transfers to and from odd address locations in memory.