Abstract: A buried junction MOS memory capacitor target device for electron beam addressable READ/WRITE memories is described along with a method of using the same. The memory capacitor target structure comprises a planar semiconductor substrate of various degrees of complexity having a highly conducting coating providing a low resistance ohmic contact to the substrate backside and an N-type planar semiconductor overlayer forming with the substrate topside a bipolar detector junction. An insulating layer overlies the N-type layer and a conducting coating overlies the insulating layer. The device is employed with an electron beam of sufficient energy to penetrate the latter two layers and to produce carrier-pairs in the N-type overlayer. Electrical access to the device is provided by one contact to the substrate backside and one contact to the conducting coating overlying the insulator.

Abstract: A method and apparatus for deep depletion read-out of data stored in a metal-insulator-semiconductor-metal capacitor memory element wherein a predetermined read-out potential is established across the memory capacitor while discrete storage sites within the capacitor are interrogated by a scanning electron beam probe and the magnitude of the resultant memory capacitor discharge current obtained from probing a particular site with the electron beam is indicative of the character of data stored at the site. The improvement comprises applying a voltage step across the capacitor memory element just prior to read-out with the electron beam, the voltage step corresponding in polarity to the polarity of the majority carriers in the semiconductor.

Abstract: A new and improved microminiature field emission electron source and method of manufacturing is described using a single crystal semiconductor substrate. The substrate is processed in accordance with known integrated microelectronic circuit techniques to form a plurality of integral, single crystal semiconductor raised field emitter tips at desired field emission cathode sites on the surface of the substrate in a manner such that the field emitter tips are integral with the single crystal semiconductor substrate. An insulating layer and overlying conductive layer may be formed in the order named over the semiconductor substrate and provided with openings at the field emission site locations to form micro-anode structures for each field emitter tip.