Abstract: A magneto-sensitive integrated circuit which amplifies a magneto-sensitive output voltage of a Hall element by an amplifier to generate an amplified voltage, converts an output voltage of the amplifier into a digital signal by an A/D converter; and generates a reference voltage of magnitude corresponding to an indicated value. The amplifier includes a voltage superposition element which superposes a DC voltage corresponding to the reference voltage on the amplified voltage to generate the output voltage of the amplifier.

Abstract: The present invention provides a memory card for use with an electronic device. The memory card comprises an input/output (I/O) interface for coupling the memory card to the electronic device and a card controller electrically coupled to the I/O interface. In particular, the card controller comprises a plurality of engines configured to operate in different formats. The card controller further comprises a means for detecting the format of the electronic device and generating a response signal containing the format of the electronic device. A micro-controller is electrically coupled to the plurality of engines, wherein the micro-controller activates an appropriate engine from the plurality of engines to transfer data based on the response signal. Furthermore, the memory comprises a memory module electrically coupled to the plurality of engines for storing data. One advantage of the memory card is that it enables a user to store and transfer data in various formats.

Abstract: A system and a method for distributing messages from mobile users over a communication network in real time. In the preferred embodiment, mobile users would enter information in handwritten form on a touch-sensitive screen using a stylus. The handwritten messages would be converted into a graphics format and then transmitted (using a suitable protocol) to a computer server. The computer server would store the graphic files in a database and also transmit the graphic files to subscribers.

Abstract: A digital audio recorder and player stores addresses of recorded audio data in at least two directories. The directories are used cyclically, address information always being read from the directory with the most recent valid address information. After a recording or editing operation, the address information read from this directory is updated, then stored in the next directory in the cycle. Each directory preferably also stores tag information identifying the directory with the most recent address information. The directories can be stored on the same digital recording medium as the audio data. This medium is, for example, a flash memory device.

Abstract: A caching apparatus and method for enhancing retrieval of data from an optical storage device are provided. The apparatus preferably includes a first memory device for storing data therein. The first memory device preferably includes a predetermined application. An optical storage device is positioned in communication with the first memory device for optically storing data therein. The optical storage device includes a plurality of data storage sectors. A second memory device is positioned in communication with the first memory device for storing data. The second memory device preferably has a predetermined amount of data storage space. The predetermined amount of data storage space includes a caching space defined by only a portion of the predetermined amount of data storage space of the second memory device.

Abstract: A floating point arithmetic unit is provided which effectuates arithmetic operations upon floating point numbers. A comparator unit, which may be implemented using a carry-skip chain, determines the relative magnitudes of the exponents of the floating point numbers to be operated upon. A first ripple carry subtractor unit formed within a first ripple carry shifter subtracts a first value corresponding to the exponent of a first of the floating point numbers from a second value corresponding to the exponent of a second of the floating point numbers. A second ripple carry subtractor unit formed within a second ripple carry shifter subtracts the second value from the first value. When certain lower order bit results of the exponent value subtraction operations of each ripple carry subtractor are obtained, the mantissa of the floating point number with the smaller exponent provided to one of the carry ripple shifters is shifted to the right by a number of positions dependent upon the lower order bit results.

Abstract: A cache including a tag storage which compares a portion of the tag address (a "mini-tag") to a respective portion of a request address is provided. If the mini-tag matches, then the way associated with the tag having a match is the way selected for conveying data bytes to the output of the cache. The mini-tag comparison is performed on a field of address bits different from the index field, and the comparison is performed in parallel with the index field decode. The way selection is qualified with the index field decode such that one set and one way of the set is selected for conveying bytes from the cache. The access time of the present cache structure is substantially similar to a direct-mapped cache. However, the present cache strucuture is a set-associative structure. The hit rate and thrashing insensitivity of a set-associative cache are maintained by the present cache.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

Abstract: An identification device is provided which includes an inactive code carrier, such as a standing acoustic wave component, a frequency mixing section, and a double antenna input. Each of the antennas are tuned to a separate predetermined transmitted signal wherein the frequencies are different. The two separately received RF frequencies are mixed to produce an intermediate frequency having the sum or difference of the two received frequencies. The intermediate frequency is coupled to the standing acoustic wave device which applies a coded signal to the intermediate frequency. The intermediate frequency is then recombined with one of the original incoming RF frequencies to be retransmitted from the identification device. The mixer section can include a diode and a coil for matching the impedance of the incoming signal with the inactive code carrier.

Abstract: A computer display screen monitoring system comprising a master station and a plurality of user stations for displaying text and graphic data appearing on one display screen in the system on one or more other display screens in the system in real time. Multiplexers are provided in each of the stations in the system for selectively transferring video as well as audio signals (when provided) between the stations in response to function codes and addresses identifying the stations.