Abstract: Disclosed by present disclosure are a self-powered power supply drive circuit and a self-powered power supply drive chip. The self-powered power supply drive circuit includes a charging detection circuit, a current sampling switch tube, a charging switch tube, a sampling circuit and a control circuit. The drive tube and current sampling switch tube, which are connected in series, are connected between the input power supply and the ground. The current sampling switch tube is switched off and the charging switch tube is switched on during the pre-switching-off stage, such that the current which flows through the drive tube during the pre-switching-off stage is used to charge the energy storage circuit. The charging time is in the pre-switching-off stage, which never affects the normal switching cycle of the drive tube itself and the normal output of energy. Moreover, this way of charging does not require any additional auxiliary coil winding.

Abstract: Disclosed is a soft-start circuit for power-up, which includes a reference value generation circuit, a protection threshold generation circuit and a control circuit. The reference value generation circuit outputs a reference value, which increases slowly, during a start-up process for power-up. The protection threshold generation circuit outputs a protection threshold, which increases slowly, during the start-up process for power-up. The control circuit controls an output voltage to increase slowly along with the reference value based on the reference value, during the start-up process for power-up, and to limit an output current based on the protection threshold to limit the output voltage, during the start-up process for power-up. In this way, even if the output current must operate at the peak current, a smoother current output is realized, and operation at the maximum peak current for a long-time during start-up is not allowed.

Abstract: Disclosed by present disclosure are a Darlington transistor drive circuit, a Darlington transistor drive method and a switching power supply management chip. In this embodiment, the Darlington transistor is driven sectionally. At the beginning of the switching-on cycle, the driving of the primary transistor is not started temporarily, instead the drive source is used to drive the secondary transistor. After the secondary transistor is completely switched on, the drive source of the secondary transistor is switched off and the drive source of the primary transistor is switched on to drive the Darlington transistor. The primary and secondary transistor have been completely switched on, and the drive current of the secondary transistor never depend on the primary transistor, so the voltage at the input terminal of the secondary transistor can be smaller than the voltage at the control terminal of the secondary transistor. Such that the switching-on power loss is reduced.

Abstract: A Buck constant voltage driver and an application circuit thereof, are disclosed. In the Buck constant voltage driver, the peripheral structure is remained unchanged for possessing the advantages of low cost and simplicity of the prior art. Meanwhile, in order to compensate the difference of output voltage caused by the change of the forward voltage drop under different output currents, an output voltage compensation module is added to the Buck constant voltage driver. The output voltage compensation module is operable to acquire an output current information based on the sampling voltage on the sampling resistor, and to compensate the preset first reference voltage according to the output current information, thus maintaining the output voltage of the Buck constant voltage driver constant, under different output current conditions.

Abstract: A chip, a self-calibration circuit and method for chip parameter offset upon power-up are disclosed. The circuit includes a counting circuit, a calibration data latch circuit, a calibration data selection circuit and a parameter calibration circuit. The counting circuit outputs a sequentially scanned counting signal when receiving a valid enabling signal. The calibration data latch circuit latches the counting signal when receiving a valid latch signal. The calibration data selection circuit selects the counting signal latched by the calibration data latch circuit as a calibration signal when receiving the valid latch signal, otherwise selects the counting signal currently outputted as the calibration signal. The parameter calibration circuit implements a parameter calibration based on the calibration signal in a calibration mode, while outputs the valid latch signal when the parameter calibration satisfies a preset requirement.

Abstract: Introduced here is a face mask system having a mask enclosure that contains, or otherwise directly supports, an automated liquid-droplet dispensing mechanism (ADM) for humidification. In operation, the enclosure and ADM are compact and lightweight so that when worn by a user can be supported entirely by the user's head and neck. The enclosure can be comprised of one or more layers of breathable fabric adapted to flexibly conform to the face of a user when worn and form a cavity that is adjacent to the user's nostrils and mouth. The ADM can be comprised of a reservoir in which liquid is stored, a respiratory cycle detector, a timer and controller, and a droplet dispenser that controllably dispenses droplets of the liquid from the reservoir into the cavity for inhalation by the user.

Abstract: A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.

Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Abstract: A constant current output charge pump includes a switch module configured to compare a reference voltage with a load voltage and output a switch signal, a voltage margin control module configured to compare a first voltage and a second voltage with an output voltage and output a voltage margin control signal, a clock control module, a charge pump module, a current control module and a load module. The clock control module is configured to capture the switch signal and the voltage margin control signal and output a first clock signal and a second clock signal according to a system to the charge pump module for charging the input voltage.

Abstract: The low-power power-on reset circuit includes a NOT gate device, a time delay device, a wave shaping device and a NOR gate device, with which the present invention can provide a low power power-on reset circuit that can be formed by a complementary metal oxide semiconductor (CMOS), such that a lower power consumption and a higher noise margin can both be provided.

Abstract: A method and apparatus wherein a material or object to be tested is placed on a base support. A stopper assembly having a stopper tip on one end in contact with the test material or object, and a washer on the opposite end attached to a rod. A projectile is propelled with a selected level of force along the rod and impacts the washer, which transmits the force of impact through the stopper tip to the test material or object. The level of propelling force, the mass of the projectile, the construction of the stopper assembly and the location of impact on the test material or object may be precisely adjusted to simulate real-life impacts.

Abstract: A method for fabricating a low dynamic resistance capacitor is an integrated circuit using conventional CMOS processing steps, where in one implementation the structure provides the additional feature of a Zener diode capable of offering ESD protection.

Abstract: An apparatus and method is provided for optimizing LED driver efficiency. The present invention offers low cost solutions for powering LEDs while minimizing overall power dissipation in devices powered by a depletable power source. Low system cost is attained using a charge pump to increase LED drive voltage level and implementing combinations of drive techniques to overcome the inefficiency of the charge pump. A switch bypasses the charge pump when depletable power source output voltage is sufficient to directly drive an LED load. At certain output voltage levels, the switch can be opened causing the charge pump to boost drive voltage. The output voltage may also be PWM modulated to drive the LED load and, at some voltages, the depletable power source may drive the LED load directly. Efficiency levels of 90-97% are attainable.

Abstract: An active termination circuit having a selective DC power consumption for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage. The circuit also has a variable current supply coupled to said first threshold reference transistor and said second threshold reference transistor arranged to reduce the DC power consumption of the active termination circuit as needed.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as stabilizing capacitors for stabilizing control node voltages.

Abstract: An active termination circuit for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device in a tri-state mode is described. The active circuit includes a tri-state output buffer and a bottom clamping transistor coupled to GND and the tri-state output buffer having a bottom clamping transistor control node arranged for clamping the signal at about GND. A bottom threshold reference transistor coupled to a first reference voltage supply configured to supply a first reference voltage. The bottom threshold reference transistor provides a first bias voltage to the bottom clamping transistor control node that biases the bottom clamping transistor control node at about a first threshold voltage above GND where the first threshold voltage represents a threshold voltage of the bottom clamping transistor.

Abstract: An active termination circuit for protecting a node against an ESD voltage spike is described. The ESD protection circuit includes a bottom ESD protection transistor having a first node coupled to a first potential and a bottom ESD protection transistor intrinsic diode reverse biasedly coupling said node to a first reference voltage supply and a bottom threshold reference transistor coupled to the first reference voltage supply. The bottom threshold reference transistor provides a first bias voltage to the bottom ESD protection transistor gate that biases the bottom clamping transistor gate at about a first threshold voltage from the first reference voltage representing a threshold voltage of said bottom ESD protection transistor.

Abstract: An active termination circuit for terminating a transmission line in bused or networked device, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor.