Patents Assigned to Micro Devices, Inc.
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Patent number: 11994939Abstract: The disclosed computer-implemented method for generating remedy recommendations for power and performance issues within semiconductor software and hardware. For example, the disclosed systems and methods can apply a rule-based model to telemetry data to generate rule-based root-cause outputs as well as telemetry-based unknown outputs. The disclosed systems and methods can further apply a root-cause machine learning model to the telemetry-based unknown outputs to analyze deep and complex failure patterns with the telemetry-based unknown outputs to ultimately generate one or more root-cause remedy recommendations that are specific to the identified failure and the client computing device that is experiencing that failure.Type: GrantFiled: September 30, 2022Date of Patent: May 28, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Mohammad Hamed Mousazadeh, Arpit Patel, Gabor Sines, Omer Irshad, Philippe John Louis Yu, Zongjie Yan, Ian Charles Colbert
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Patent number: 11996166Abstract: A technique for processing computer instructions is provided. The technique includes obtaining information for an instruction state memory entry for an instruction; identifying, for the instruction state memory entry, a slot in an instruction state memory having selectably powered rows and blocks, based on clustering criteria; and placing the instruction state memory entry into the identified slot.Type: GrantFiled: August 29, 2019Date of Patent: May 28, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Fataneh Ghodrat, Tien E. Wei
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Patent number: 11995149Abstract: A processing system includes a first set and a second set of general-purpose registers (GPRs) and memory access circuitry that fetches nonzero values of a sparse matrix into consecutive slots in the first set. The memory access circuitry also fetches values of an expanded matrix into consecutive slots in the second set of GPRs. The expanded matrix is formed based on values of a vector and locations of the nonzero values in the sparse matrix. The processing system also includes a set of multipliers that concurrently perform multiplication of the nonzero values in slots of the first set of GPRs with the values of the vector in corresponding slots of the second set. Reduced sum circuitry accumulates results from the set of multipliers for rows of the sparse matrix.Type: GrantFiled: December 17, 2020Date of Patent: May 28, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sateesh Lagudu, Allen H. Rush, Michael Mantor
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Patent number: 11996848Abstract: The disclosed computer-implemented method includes providing, by a reference clock circuit, a clock signal for a clock-triggered element triggered by the clock signal and modulating, by a frequency modulation circuit, a frequency of the clock signal. The method also includes inserting, by a phase compensation circuit, a phase compensation offset to the modulated clock signal in a manner that compensates for a phase error produced by modulating the frequency of the clock signal. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: November 2, 2022Date of Patent: May 28, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Aaron D. Willey, Karthik Gopalakrishnan
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Patent number: 11995351Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.Type: GrantFiled: November 1, 2021Date of Patent: May 28, 2024Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Joseph L Greathouse, Sean Keely, Alan D. Smith, Anthony Asaro, Ling-Ling Wang, Milind N Nemlekar, Hari Thangirala, Felix Kuehling
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Patent number: 11995008Abstract: A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.Type: GrantFiled: June 22, 2021Date of Patent: May 28, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Guanhao Shen, Ravindra Nath Bhargava, James R. Magro, Kedarnath Balakrishnan
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Publication number: 20240168639Abstract: An apparatus for performing distributed reduction operations using near-memory computation includes memory and a first near-memory compute node. The first-near-memory compute node is coupled to a plurality of near-memory compute nodes. The first near-memory compute node comprises logic to store first data loaded from a second near-memory compute node, perform a reduction operation on the first data and second data to compute a result; and store the result within the first near-memory compute node. In some aspects, the near-memory compute node includes a PIM execution unit and carries out the reduction operation utilizing PIM commands.Type: ApplicationFiled: November 18, 2022Publication date: May 23, 2024Applicant: ADVANCED MICRO DEVICES, INC.Inventors: SHAIZEEN AGA, JOHNATHAN ALSOP, NUWAN JAYASENA
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Publication number: 20240168513Abstract: A disclosed technique includes clock gating a plurality of data elements of a first clock domain of a scan dump network; outputting data from a plurality of data elements of a second clock domain of the scan dump network; clock gating the plurality of data elements of the second clock domain; and outputting data from the plurality of data elements of the first clock domain.Type: ApplicationFiled: November 18, 2022Publication date: May 23, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Nehal Patel
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Publication number: 20240169641Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include providing indices and vertices to a culling shader; culling primitives and outputting primitives and indices that are not culled; and generating information for a fine binning pass based on the indices and primitives that are not culled.Type: ApplicationFiled: March 31, 2023Publication date: May 23, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vishrut Vaibhav, Michael John Livesley, Tad Robert Litwiller
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Publication number: 20240171918Abstract: A MEMS element comprises a substrate 1 with an opening 1a, a vibrating membrane 3 formed on the substrate 1 through an insulating film 2, and a backplate 5 fixed to a spacer 4 on the substrate 1. The vibrating membrane 3 has intermittent slits 3a along its edge 3d. The backplate 5 has acoustic holes 5b in the center, and etching holes 5c in the periphery thereof and closer to the edge side than the outermost peripheral end of the slits of the vibrating membrane 3 in planar view. The edge 3d of the vibrating membrane 3 and portion of the insulating film 2 under the vibrating membrane 3 are spaced apart from the bottom end of the spacer 4. The insulating film is etched from the edge 3d of the vibrating membrane 3 and the slits 3a to under the vibrating membrane 3.Type: ApplicationFiled: March 23, 2021Publication date: May 23, 2024Applicant: Nisshinbo Micro Devices Inc.Inventors: Takao FUKUTOME, Yoshimitsu KARASAWA
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Patent number: 11989144Abstract: Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the interrupts to the processor and operating system responsible for handling interrupts. Each interrupt source embeds an ID when conveying an interrupt to the interrupt controller. This allows the interrupt controller to differentiate between the interrupt sources and to identify which source generated a given interrupt. The interrupt controller conveys an indication of the source of the interrupt to the processor when forwarding the interrupt to the processor.Type: GrantFiled: July 30, 2021Date of Patent: May 21, 2024Assignee: Advanced Micro Devices, Inc.Inventors: HaiKun Dong, ZengRong Huang, Ling-Ling Wang, MinHua Wu, Jie Gao, RuiHong Liu
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Patent number: 11989050Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.Type: GrantFiled: December 29, 2021Date of Patent: May 21, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Deepesh John
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Patent number: 11989591Abstract: A dynamically configurable overprovisioned microprocessor optimally supports a variety of different compute application workloads and with the capability to tradeoff among compute performance, energy consumption, and clock frequency on a per-compute application basis, using general-purpose microprocessor designs. In some embodiments, the overprovisioned microprocessor comprises a physical compute resource and a dynamic configuration logic configured to: detect an activation-warranting operating condition; undarken the physical compute resource responsive to detecting the activation-warranting operating condition; detect a configuration-warranting operating condition; and configure the overprovisioned microprocessor to use the undarkened physical compute resource responsive to detecting the configuration-warranting operating condition.Type: GrantFiled: September 30, 2020Date of Patent: May 21, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Anthony Gutierrez, Vedula Venkata Srikant Bharadwaj, Yasuko Eckert, Mark H. Oskin
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Patent number: 11989918Abstract: Systems, apparatuses, and methods for converting pixel data to a custom swizzle mode are disclosed. A graphics engine receives data in a pre-defined swizzle mode. The graphics engine determines a custom swizzle mode for the data that has directionality aligned to the data itself to further optimize deltas that are used for compressing the data. The graphics engine groups incoming data into group of two neighboring pixels in both the horizontal and vertical directions. The graphics engine scores horizontal and vertical groupings against each other to make a first swizzle mode bit selection. Then the graphics engine increases the grouping of pixels to include additional pixels and scores the increased groupings against each other to make subsequent swizzle mode bit selections. The data is reswizzled into the custom swizzle mode and provided to a compressor to be compressed.Type: GrantFiled: December 23, 2020Date of Patent: May 21, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Nooruddin Ahmed, Anthony Chan, Christopher J. Brennan
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Publication number: 20240163564Abstract: A method and apparatus for normalizing an image in an image capturing device includes receiving a processed image by the image device. The processed image is brightness normalized to create a brightness normalized image. The brightness normalized image is provided to an artificial intelligence engine for processing.Type: ApplicationFiled: November 16, 2022Publication date: May 16, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Chang-Chiang Lin
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Patent number: 11983624Abstract: Systems, apparatuses, and methods for implementing an auto generation and tuning tool for convolution kernels are disclosed. A processor executes multiple tuning runs of a given layer of a neural network while using a different set of operating parameter values for each tuning run. The operating parameters can include one or more of input dataset fetch group size, output channel group size, and other parameters. The processor captures performance data for each tuning run and then after all tuning runs have finished, the processor determines which set of operating parameter values resulted in a better performance for the given neural network layer. The processor uses these operating parameter values for subsequent iterations of the given layer. The processor also performs the same techniques for other layers to determine which set of operating parameter values to use for each layer so as to maximize performance of the neural network.Type: GrantFiled: March 27, 2019Date of Patent: May 14, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Jian Yang
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Patent number: 11984175Abstract: The disclosed method may include detecting, by a control circuit coupled to a first read only memory (ROM) device and a second ROM device, a failure of a first output signal from the first ROM device to a common output. The first ROM device is connected to the common output and the second ROM device is disconnected from the common output. The method also includes switching, by the control circuit in response to detecting the failure, the common output from the first ROM device to the second ROM device. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: June 30, 2022Date of Patent: May 14, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Cai YongFeng
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Patent number: 11983560Abstract: Systems, apparatuses, and methods for efficient parallel execution of multiple work units in a processor by reducing a number of memory accesses are disclosed. A computing system includes a processor core with a parallel data architecture. One or more of a software application and firmware implement matrix operations and support the broadcast of shared data to multiple compute units of the processor core. The application creates thread groups by matching compute kernels of the application with data items, and grouping the resulting work units into thread groups. The application assigns the thread groups to compute units based on detecting shared data among the compute units. Rather than send multiple read access to a memory subsystem for the shared data, a single access request is generated. The single access request includes information to identify the multiple compute units for receiving the shared data when broadcasted.Type: GrantFiled: January 7, 2022Date of Patent: May 14, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Li Peng, Jian Yang, Chi Tang
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Publication number: 20240152434Abstract: A device for disabling faulty cores using proxy virtual machines includes a processor, a faulty core, and a physical memory. The processor is responsible for executing a hypervisor that is configured to assign a proxy virtual machine to the faulty core. The assigned proxy virtual machine also includes a minimal workload. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: November 6, 2023Publication date: May 9, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Srilatha Manne
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Patent number: 11977757Abstract: Profile switching for memory overclocking is described. In accordance with the described techniques, a memory is operated according to a first memory profile. During operation of the memory according to the first memory profile, a request is received to operate the memory according to a second memory profile. Responsive to the request, operation of the memory is switched to operate according to the second memory profile without rebooting. In one or more implementations, at least one of the first memory profile or the second memory profile comprises an overclocking memory profile that configures the memory to operate in an overclocking mode. In one or more implementations, the memory is trained to operate according to the overclocking memory profile prior to operating the memory according to the first memory profile.Type: GrantFiled: April 29, 2022Date of Patent: May 7, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Grant Evan Ley, Jayesh Hari Joshi, Amitabh Mehra, Jerry Anton Ahrens, Joshua Taylor Knight, Anil Harwani, William Robert Alverson