Abstract: A radio transceiver comprises a reception path, a transmission path, and a frequency generator with a programmable phase lock loop. The reception path, the transmission path, and the frequency generator share a maximum amount of common circuitry to facilitate implementation of the entire radio transceiver on a single integrated circuit. The reception path includes an amplifier and a quadrature mixer for producing low intermediate frequency signals. The transmission path can be controlled by either a modulated voltage controlled transmitter or an in-phase and quadrature modulator transmitter.

Abstract: The mixer circuit is a singled ended input to a double balanced high dynamic range mixer with only two base-emitter junctions across the supply. It provides for the use of bondwires to off chip ground as DC block and DC feed elements. The single ended input and differential output balanced mixer is well suited for the input stage of an integrated radio receiver—off chip circuitry is usually single ended, but on chip circuits are usually differential. No off chip differential RF circuits or baluns are required which reduces off chip component count and improves radio performance. The mixer circuit has lower LO drive requirements because of the DC coupled LO port. This results in better radio performance and a smaller die area because of the DC coupled IF port.

Abstract: A data recovery algorithm for implementation in a radio transmitter or receiver that includes a direct current level setting circuit with a preamble detector which will establish a threshold for a simplified decision simplified equalizer slicer that improves receiver performance in a feedback manner by utilizing an analog comparator, a one symbol long one bit resolution delay line and a summing junction.

Abstract: A fuse-trimmed tank circuit for an integrated voltage-controlled oscillator (VCO). The tank circuit includes an L-C portion; a cross-coupled pair of transistors, whose collectors are coupled to the L-C portion; a capacitor coupled across the emitters of the cross-coupled pair of transistors; and a pair of resistors, where each resistor is coupled between a corresponding one of the emitters and a ground node. This oscillator circuit provides improved performance over prior oscillator circuits. A technique for trimming the VCO is utilized to adjust its center frequency. Capacitance for the L-C portion of the tank circuit is provided by one or more varactor diodes. When the VCO is operational, the varactors are reverse biased and, thus, act as capacitive elements. One or more of the varactors has an associated fuse coupled in series with the corresponding varactor. To trim the center frequency of the VCO, the capacitance of the L-C portion is adjusted by selectively blowing the fuses.

Abstract: The invention is an improved implementation of an active-RC polyphase band-pass filter with transconductor cross-coupling between filter sections. The polyphase filter has first to fourth inputs, first to fourth outputs, two filter sections, and a block of transconductor pairs. The four input signals to the polyphase filter succeed one another in phase by 90 degrees. The two filter sections have reactances comprised of active balanced operational amplifiers with matched capacitors in their feedback loops. The block of transconductor pairs is coupled between corresponding reactances of each filter. The transconductance of each transconductor pair is set as the product of a desired radian center frequency and the capacitance of the corresponding matched capacitors. In the preferred embodiment, the transconductors are Gm cells and the transconductance of at least one Gm cell is field adjustable.

Abstract: A technique for interfacing transmission media in a local area network (LAN). A first transceiver and a second transceiver, each have a media dependent interface and a media independent interface. Each media dependent interface is coupled to respective transmission media while the media independent interfaces are coupled together. A receive clock output of the first transceiver is coupled to a first input of a first multiplexer. A receive clock output of the second transceiver is coupled to a first input of a second multiplexer. A fixed frequency clock signal is coupled to a second input of the first multiplexer and to a second input of the second multiplexer. An output of the first multiplexer is coupled to a reference clock input of the second transceiver. An output of the second multiplexer is coupled to a reference clock input of the first transceiver. A select input of the first multiplexer is coupled to a status output of the first transceiver.

Abstract: A method and apparatus for modulation of a voltage-controlled oscillator (VCO). The VCO receives a tuning control voltage for adjusting a center frequency of an output periodic signal formed by the VCO. In addition, the VCO receives a modulation control voltage for modulating the output periodic signal by a content-carrying signal according to frequency modulation techniques. A frequency deviation obtained in the output periodic signal in response to changes in the modulation control voltage is linearized by forming the modulation control voltage as the result of a linear correction polynomial. A linear correction circuit forms the modulation control voltage. More particularly, a first amplifier having a gain of K1 receives the tuning control voltage. A first summing block then receives the output of the first amplifier and adds the constant K0. A second amplifier having a gain of m receives the content-carrying signal.

Abstract: An current share controller detects a power converter module having the lowest supply current. That lowest supply current converter module is selected to be the system master. The current share controller is configured such that shared devices within the system can hot-swap capability. An output voltage loop amplifier includes an opto-coupler driver. The voltage loop amplifier compensation is compatible with conventional TL431 shunt regulators. This allows a power supply system to balance supply current between multiple supply modules with an eight pin load balancer configuration.

Abstract: A method and apparatus for controlling the operation of a gas discharge lamp including regulation of power provided to the lamp for maintaining a preselected illumination intensity, automatic lamp shut down for preventing a catastrophic failure of the lamp, and automatic selection of operating frequencies for increasing efficiency and extending useful life of the lamp. An appropriate quality factor Q is achieved by including a low pass filter followed by a high pass filter in the lamp network so as to allow deep dimming of the lamp. Preferably, the arc power delivered to the lamp network is sensed and regulated. By sensing the arc power instead of only the lamp current, the illumination intensity of the lamp is accurately regulated. Further, the lamp ballast is automatically shut down near the end of the lamp's useful life, before operation in partial rectification.

Abstract: A delay cell for use within a voltage controlled oscillator capable of operating at two different selectable frequencies, the delay cell having a first delay stage including a first differential pair of transistors, wherein the emitter or each transistor is coupled to a first common node and further wherein a first current exiting the first common node is selectively variable. The delay cell further having a second delay stage including a second differential pair of transistors, each having an emitter coupled to a second common node wherein a second current exiting the second common node is selectively variable and wherein a sum of the first current and the second current is substantially constant. The amount of delay associated with the first delay stage is dependent upon the level of the first current.

Abstract: The present invention is a CML to CMOS converter which includes a bipolar input stage, a current source/current sink stage, and an output stage. The converter is able to transfer a CML input voltage differential to a CMOS compatible voltage having constant high and low voltage levels with a constant duty cycle. The bipolar input stage receives an incoming CML voltage differential and steps the voltage levels down. Utilizing the stepped down CML voltage differential, the current/source sink drives the output stage by maintaining an equal current source and current sink to and from the output stage, ensuring that an output voltage at the output stage rises and falls to constant high and low voltage levels, thereby maintaining a constant duty cycle. A first pair of NMOS transistors, coupled to the output stage drive current to the output stage from a high input voltage rail whenever the input differential is high.

Abstract: A modular power supply which distributes responsibility for supplying current to a load among two or more power supply modules having a common output node. One of the power supply modules which supplies the lowest level of current to the load functions as the master while the remaining power supply modules each function as a slave. A load share bus which interconnects all the power supply modules is driven by the master with a signal representative of the level of current supplied by the master. Each slave module attempts to reduce its output current to a level which is a predetermined offset above the level of current supplied by the master while a regulated voltage is maintained at the common output node. Any one of the modules can become the master, though once the system is operating, the predetermined offset generally prevents the roles from changing. Should one of the power supply modules fail such that its output current is uncontrolled, this power supply module will not be the master.

Abstract: A two-stage differential to single-ended amplifier. The input stage converts a differential voltage to a differential current. A first pair of bipolar input transistors are biased with constant currents. Therefore, their on-resistance does not affect gain linearity. Changes in input voltages induce currents in a first pair of field effect transistors (FETs) each having a gate coupled to the collector of a corresponding input transistor and a drain coupled to the emitter of the corresponding input transistor. Differential currents are provided to the output stage by a second pair of FETs, each configured to mirror the current in a corresponding one of the first pair of FETs. Gain is adjustable by enabling additional pairs of FETs configured as current mirrors. The output stage includes a second pair of bipolar transistors with bases coupled together and biased with equal currents. Currents from the input stage are applied to the emitters of the second pair of bipolar transistors.

Abstract: A method and apparatus for interleaving switching of multiple transistor switches in a power factor correction (PFC) boost converter and for timing the switching to occur when a current through a freewheeling diode corresponding to each switch is at a minimum level. The converter draws input current from an alternating current power supply for forming a regulated output voltage. A controller senses an input current and an output voltage across an output capacitor for controlling switching to regulate the output voltage and to ensure that the input current is substantially in phase with an input voltage. Current through a first inductor associated with a first switch is allowed to fall substantially to zero upon discharging the first inductor prior to re-charging the first inductor. Charging of a second inductor associated with a second switch, however, is initiated prior to completion of discharging the first inductor.

Abstract: The present invention provides two or more output voltages from one input voltage and one inductor. Each output voltage is formed by a switch controlling the charge delivered to each of the corresponding output capacitors. Preferably, a diode is placed in series with each switch that controls the charging of the output capacitors to prevent any extraneous stray current from escaping while the switch is closed. The controller utilizes pulse width modulation to deliver the correct amount of energy to each load and to synchronize the order of energy delivery to each load. The use of one input voltage and one inductor for charging multiple output voltages simplifies the complexity of the circuit of the present invention and eliminates the need for a single inductor dedicated to each load. Further, the predetermined output voltage level for each load can be changed without modifying the passive elements in the circuit.

Abstract: A circuit that senses a current signal in a secondary winding of a transformer by monitoring a current signal in a primary winding of the transformer. The monitored current signal contains an effective current component and a magnetization current component. The magnitude of the effective current signal is related to the magnitude of the current signal in the secondary winding by the turns ratio of the transformer. The magnetization current signal produces flux in the transformer core and does not contribute to producing current in the secondary winding of the transformer. In addition, the magnetization current is 90 degrees out of phase with the effective current signal in the primary winding. The effective current signal in the primary winding is in phase with the voltage signal applied to the primary winding. The invention integrates the monitored current signal over 0 degrees to 180 degrees of the effective current signal waveform.

Abstract: A battery power conversion circuit comprising a cell equalization circuit that ensures that each cell in a multiple battery cell stack is depleted of charge at an equal rate. The stack is coupled to provide current to a primary winding of a transformer. Each of the nodes between cells is coupled to the primary winding of the transformer through a transistor such that an equal number of turns of the primary winding are present between each node. An additional transistor coupled in series with the primary winding controls the current through the primary winding such that a capacitor coupled to a secondary winding of the transformer may be charged by an induced secondary current to a desired voltage level for powering a load. A controller circuit monitors the output voltage level and controls the transistor in series with the primary winding for maintaining the desired load voltage through a feedback loop.

Abstract: A two-stage switching regulator having low power modes responsive to load power consumption. A first stage of the regulator is a power factor correction (PFC) stage. A second stage is a pulse-width modulating (PWM) stage. When a load draws a high level of current, switching in both stages is enabled. Under certain conditions, switching in either one or both of the stages is disabled by the duty cycle for the corresponding switch falling to zero. When switching in both stages is enabled, as in a normal mode, switching in the PWM stage is then disabled in response to an error signal falling below a first error threshold. When switching in the PFC stage is enabled and switching in the PWM stage is disabled, as in a first low power mode, switching in the PFC stage is then disabled in response to a feedback voltage rising above a first feedback threshold.

Abstract: A circuit that forms a square wave pulse train signal wherein each pulse is centered about a zero crossing of a reference sinusoid. A first capacitor is coupled to be charged and discharged at equal rates by a first transconductance amplifier. Upon a first positive zero crossing of the reference sinusoid, the first transconductance amplifier begins charging the first capacitor. Upon the first negative zero crossing, the first transconductance amplifier begins discharging the first capacitor until a first predetermined voltage level is reached. Upon reaching the first predetermined voltage level, the first transconductance amplifier begins charging the first capacitor again. The voltage on the first capacitor is compared by a first comparator to a second predetermined voltage level higher than the first voltage level. The output of the first comparator is a pulse which is centered about a second positive zero voltage crossing of the reference sinusoid.

Abstract: A controlled output voltage is provided for a switching mode power converter operating in the continuous conduction mode without requiring a feedback path coupled to monitor the output voltage. Instead, a voltage related to the input voltage is monitored. The monitored voltage is compared to a periodic waveform for forming a switch control signal. In the case of a buck converter operating as a voltage regulator, over each period of the periodic waveform, the periodic waveform is representative of the inverse function. In the case of a boost converter operating as a voltage regulator or buck converter operating as a bus terminator or power amplifier, over each period of the periodic waveform, the periodic waveform has a linear slope. The switch control signal controls a duty cycle of the power switches. Therefore, switching is controlled in an open loop, rather than in a closed loop.