Abstract: This document describes a new op-amp sharing technique for pipeline ADC without memory effect. The key features of this technique are: the usage of negative impedance converter and scaled replica of the op-amp input device to achieve zero error voltage, which in turns achieve low power dissipation due to the removal of the tradeoff between op-amp sharing and memory effect. With this technique much lower operation of pipeline ADC can be achieved for applications of data communications and image signal processing.

Abstract: A microcontroller chip with a central processing unit (CPU) is adapted to control an external system with which the device is to be installed in circuit. The microcontroller chip includes an on-chip peripheral universal timing function module with a register for storing a value selected to signify a distinctive event in a waveform. A timer generates a series of values as a function of time as a measure of the value selected to signify the distinctive event. The register and the timer are coupled to a pin of the microcontroller chip on which said waveform is to be applied. Equality between the values in the timer and the register signify the distinctive event as one of a capture and a compare of an event in the waveform, to generate an interrupt to the CPU.

Abstract: An I.sup.2 C bus-compatible, serial EEPROM device is used in applications involving storage and serial transmission of configuration and control information for an intelligent peripheral device with which the EEPROM device is associated, for communication on a bus to a host device adapted to control the peripheral device. The EEPROM device has a memory array for storing data representing the configuration and control information. Two modes of data transmission are supported by the EEPROM device, and are alternately and selectively established according to whether data stored in the EEPROM array is to be read only, by sequential output onto the bus, or the array is also to be allowed to be written to. The arrangement ultimately allows intelligent interaction between the host device and the peripheral device. A separate clock line supplements the usual clock line and data line of an I.sup.2 C bus to support the distinct and different modes, with clocking by the respective clock line for the established mode.