Abstract: Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.

Abstract: A serial communication link receiver-transmitter with autonomous transmission error detection is described, and a communication peripherals including the same. Transmit data at a transmitter and transmitted data output by the transmitter and received by the receiver are observed by an error detector configured to generate an error indication in response to difference between the transmit data and corresponding observed transmit data of a transmitted data frame. If a difference is detected a transmit error indicator is asserted.

Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

Abstract: A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.

Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

Abstract: Object detection for wireless power transmitters and related systems, methods, and devices are disclosed. A controller for a wireless power transmitter is configured to receive a measurement voltage potential responsive to a tank circuit signal at a tank circuit, provide an alternating current (AC) signal to each of the plurality of transmit coils one at a time, and determine at least one of a resonant frequency and a quality factor (Q-factor) of the tank circuit responsive to each selected transmit coil of the plurality of transmit coils. The controller is also configured to select a transmit coil to use to transmit wireless power to a receive coil of a wireless power receiver responsive to the determined at least one of the resonant frequency and the Q-factor for each transmit coil of the plurality of transmit coils.

Abstract: An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

Abstract: A metal-insulator-metal (MIM) capacitor module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode conductively coupled to the bottom electrode base, a planar insulator formed over the bottom electrode, and a top electrode formed in an upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component.

Abstract: Some embodiments of the present disclosure may include a controller for an object-recognition system. The controller may include a capacitive-sensor-button controller configured to provide a button-status report at least partially responsive to proximity of the object to specified areas of a capacitive sensor. The controller may also include a recognizer configured to generate an object identifier at least partially responsive to the button-status report when an object having a plurality of detectable elements in a predetermined spatial pattern is in proximity thereof. Some embodiments of the present disclosure may include a controller for an object-recognition system. The controller may include a reader configured to capture channel-capacitance measurements of a capacitive sensor.

Abstract: A charge compensation circuit is disclosed that provides amplified charge cancellation. A touch controller is disclosed that includes such a charge compensation circuit and may realize improved immunity to baseline capacitance signals that are much larger than a change in capacitance due to proximity of an object. Such a charge compensation circuit may include a capacitor, a driver circuit arranged to apply a pulsed voltage signal to the capacitor, and a current conveyor having a programmable gain and arranged to amplify an initial charge generated by the capacitor in response to the pulsed voltage signal and provide an amplified charge to an output of the charge cancellation circuit.

Abstract: An apparatus includes a graphics driver circuit and a graphics engine circuit. The graphics engine circuit is configured to determine graphics data to be output to a display and to render the graphics data to a buffer. The graphics driver circuit is configured to output the buffer to the display. The graphics engine circuit is further configured to, while the graphics driver circuit is outputting the first buffer to the display, encode the first graphics data into another buffer, and to signal the graphics driver circuit to output the other buffer to the display.

Abstract: A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.

Abstract: An electronic fuse (e-fuse) module may be formed in an integrated circuit device. The e-fuse module may include a pair of metal e-fuse terminals (e.g., copper terminals) and an e-fuse element formed directly on the metal e-fuse terminals to define a conductive path between the pair of metal e-fuse terminals through the e-fuse element. The metal e-fuse terminals may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The e-fuse element may be formed by depositing and patterning a diffusion barrier layer over the metal e-fuse terminals and interconnect elements formed in the metal interconnect layer. The e-fuse element may be formed from a material that provides a barrier against metal diffusion (e.g., copper diffusion) from each of the metal e-fuse terminals and interconnect elements. For example, the e-fuse element may be formed from titanium tungsten (TiW) or titanium tungsten nitride (TiW2N).

Abstract: An electronic device includes an integrated circuit package including a die mounted on a die carrier, a mold structure at least partially encapsulating the mounted die, and a heat transfer chimney formed on the die. The heat transfer chimney extends at least partially through the mold structure to transfer heat away from the die. The heat transfer chimney is formed from a thermally conductive compound including thermally conductive nanoparticles.

Abstract: Analog signal measurement and related circuitry, systems, and methods are disclosed. Circuitry includes timing circuitry configured to assert a first enable signal at a first time and a second enable signal at a second time. The circuitry also includes an operational amplifier circuit configured to enable responsive to the assertion of the first enable signal. The operational amplifier circuit is configured to receive an analog input signal and, if enabled, generate an amplified analog input signal responsive to the analog input signal. The circuitry further includes signal analyzing circuitry configured to enable responsive to the assertion of the first enable signal, compare the amplified analog input signal to one or more threshold values responsive to the assertion of the second enable signal, and generate an alert signal responsive to a determination that the amplified analog input signal falls outside of the one or more threshold values.

Abstract: Embodiments of the disclosure relate, generally, to techniques for parallel acquisition and measurements and related circuits, systems and devices that implement those techniques. A technique for parallel acquisition and measurement generally includes simultaneously acquiring sensed signals from multiple sensor channels and determining which sensed signal of the acquired sensed signals has the largest relative contribution to a measurement.

Abstract: A method of forming a via is provided. A lower metal element is formed, and a first patterned photoresist is used to form a sacrificial element over the lower metal element. A dielectric region including a dielectric element projection extending upwardly above the sacrificial element is formed. A second patterned photoresist including a second photoresist opening is formed, wherein the dielectric element projection is at least partially located in the second photoresist opening. A dielectric region trench opening is etched in the dielectric region. The sacrificial element is removed to define a via opening extending downwardly from the dielectric region trench opening. The dielectric region trench opening and the via opening are filled to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.

Abstract: Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.

Abstract: Various embodiments relate to a voltage converter including a control unit configured for operating in a hysteretic control mode. A control unit may be configured to receive a PWM signal, a duty cycle signal, at least one reference voltage, a factor of an output voltage of the voltage converter, and a factor of an input voltage of the voltage converter. The control unit may also be configured to compare the at least one reference voltage to the factor of the output voltage and the factor of the input voltage. Further, the control unit may be configured to generate a first control signal mirroring the PWM signal in response to at least one of: the factor of the input voltage being greater than the at least one reference voltage and the factor of the output voltage being greater than the at least one reference voltage.