Abstract: An access system includes a transmitter and a receiver for exchange of secure data wherein the system uses an encryption and a decryption algorithm to exchange a secure data packet. The secure data packet may include an unencrypted data packet and an encrypted data packet. The encrypted data packet may include first data encrypted by the encryption algorithm, and data decrypted by the decryption algorithm, wherein the data decrypted by the decryption algorithm includes a combination of a secure signature and second data encrypted by the encryption algorithm.

Abstract: A voltage regulator for controlling an output device in accordance with embodiments includes an error amplifier; a controlled conductance output device; and a load predicting circuit; wherein an output of the error amplifier and an output of the load predicting circuit are summed to control the output device.

Abstract: An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer.

Abstract: Power converters typically have unique circuitry for graceful start-up and to develop correct operating voltage biases. Typically this unique circuitry is incorporated into a primary-side “start-up” controller. This start-up controller can also be the primary means of control of the power converter once started. However, a secondary-side controller is typically needed for more exact output voltage regulation, duplicating circuitry already present in the primary-side start-up controller. During light-load or no load conditions, on and off switching of the gate driver is stopped when the secondary-side controller sends a standby code inhibit (disable) command to the start-up controller. When power needs to be sent to the secondary side of the transformer to charge a secondary side capacitor, the secondary-side controller sends an enable code command to the start-up controller where it is detect to allow the start-up controller to operate in a normal fashion with the secondary side controller.

Abstract: A series-parallel resonant power converter comprises a primary-side start-up controller and a secondary-side controller, wherein the primary-side start-up controller sends power to the secondary-side controller when power (voltage) is first applied to the series-parallel resonant power converter. The start-up controller starts up the series-parallel resonant power converter using an open-loop start-up technique wherein the secondary-side closed-loop controller takes over control of the series-parallel resonant power converter once it becomes powered and activated. During light-load or no load conditions, the secondary-side controller sends an off resonance higher frequency or a standby code inhibit (disable) command to the start-up controller.

Abstract: A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.

Abstract: An integrated temperature sensor device has a temperature sensor configured to provide an analog signal corresponding to an ambient temperature, an analog-to-digital converter receiving the analog signal and a programmable digital filter coupled to the analog-to-digital converter.

Abstract: The average of a complex waveform measured over a time period may be determined by first converting the complex waveform to a voltage, then converting this voltage to a current and using this current to charge a capacitor. At the end of the measurement time period the voltage charge (sample voltage) on the capacitor may be sampled by a sample and hold circuit associated with an analog-to-digital converter (ADC). Then the voltage charge on the sample capacitor may be removed, e.g., capacitor plates shorted by a dump switch in preparation for the next average of the complex waveform sample measurement cycle. The ADC then converts this sampled voltage charge to a digital representation thereof and a true average of the complex waveform may be determined, e.g., calculated therefrom in combination with the measurement time period.

Abstract: A light emitting diode (LED) lamp circuit is adapted to replace a fluorescent lamp in a fluorescent light fixture without having to modify the fluorescent light fixture in any way. The LED light string and its associated drive circuitry may be divided into two symmetric light strings. Furthermore, the two strings (power rails more precisely) may be tied together with a diode voltage/current steering system. The fluorescent replacement LED lamp design ‘spoofs’ all fluorescent lamp drive modes that a ballast could be configured for.

Abstract: An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time

Abstract: An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.

Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

Abstract: A USB smart hub may provide enhanced battery charging, data storage security, vendor matching, device authentication, data capture/debug, and role switching. The smart hub may include an upstream port, a plurality of downstream ports, a processor, and a memory coupled to the processor for storing USB host stack code and configuration parameters. The smart hub may include a USB hub core having a core to implement a standard USB hub interface. The smart hub may include a plurality of 2:1 multiplexors coupled between the downstream ports, the core downstream ports, and the processor. The processor may control the 2:1 multiplexors. The processor may be configured to detect when a USB device is coupled to a downstream port and to run the USB host stack code and to enumerate the USB device. The processor may provide enhanced features based on the configuration parameters.

Abstract: An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.

Abstract: A capacitive sensor system has a receiving electrode with a capacitive coupling to a ground plane or ground electrode, a first transmission electrode arranged between the receiving electrode and the ground plane and having a size with respect to the receiving electrode such that the transmission electrodes covers a surface area of the receiving electrode, and a second transmission electrode arranged adjacent to the receiving electrode and which is not coupled with the first transmission electrode, wherein the second transmission electrode is driven with a higher alternating voltage than the first transmission electrode.

Abstract: A spacer etching process produces ultra-narrow polysilicon and gate oxides for insulated gates used with insulated gate transistors. Narrow channels are formed using dielectric and spacer film deposition techniques. The spacer film is removed from the dielectric wherein narrow channels are formed therein. Insulating gate oxides are grown on portions of the semiconductor substrate exposed at the bottoms of these narrow channels. Then the narrow channels are filled with polysilicon. The dielectric is removed from the face of the semiconductor substrate, leaving only the very narrow gate oxides and the polysilicon. The very narrow gate oxides and the polysilicon are separated into insulated gates for the insulated gate transistors.

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region, and forming first and second electrolyte regions and first and second top electrodes over the bottom electrode to define distinct first and second memory elements. The first memory element defines a first conductive filament/vacancy chain path from the first portion of the bottom electrode pointed tip region to the first top electrode via the first electrolyte region, and second memory element defines a second conductive filament/vacancy chain path from the second portion of the bottom electrode pointed tip region to the second top electrode via the second electrolyte region.

Abstract: A display with an inner visible display area and an outer support area which does not provide a display function is enhanced with an electrode arrangement. The electrode arrangement provides for a substrate layer on which a transmitting electrode is arranged which is surrounded by a plurality of receiving electrodes, wherein at least the transmit electrodes is transparent and at least partially covers the inner visible display area and the receiving electrodes are arranged on portions of the substrate layer covering the outer support area.

Abstract: A combination of a precision analog-to-digital converter (ADC), an analog amplifier having selectable gains and an intelligent controller to coordinate the amplifier gain selection and placement of the digital conversion results into at least one register provide for a very high resolution analog-to-digital conversion process, at a high sample rate and low power consumption. For example, a 14-bit ADC may be used with selectable gain analog amplification, e.g., ×1, ×2, ×4 and ×8, between the sampled signal and ADC input and an intelligent controller to provide a 17-bit conversion number having proper scaling of the digital sample words. The entire high resolution analog-to-digital conversion process may be automatically performed without additional control from external hardware/software.

Abstract: A voltage regulator has a large gm current buffer driver added between a first stage of an operation amplifier and a last stage power transistor. This current buffer allows a significant reduction in the maximum internal and external compensation capacitances needed for regulator stability. The current buffer compensation circuit allows a wide range of external capacitor sizes that increases the flexibility in choosing the external capacitor types (with low to high ESR ratings).