Abstract: A phase-locked loop (PLL) circuit which receives a signal at a reference frequency to generate a spread spectrum clock signal. A first divider circuit in the PLL and connected to the PLL input terminal generates an output signal at the reference frequency divided by a first variable integer M. A second divider circuit connected to the PLL output terminal generating an output signal at the output frequency divided by a second variable integer N. The PLL also has a circuit which periodically varies the first variable integer M and the second variable integer N. This permits the frequency of the output signal to vary precisely between two predetermined frequencies to spread the spectrum of output frequencies.