Abstract: The present invention provides for a voltage-controlled crystal oscillator (VCXO) which, other than the crystal itself, is full integrated. The VCXO has a pre-amplifier block, a gain stage, a first MOS transistor, a first capacitor, a second MOS transistor, and a one second capacitor. The pre-amplifier block receives an input tuning voltage and the gain stage is connected across the terminals of the oscillating crystal. The first MOS transistor and first capacitor are connected between one of the terminals of the oscillating crystal and a reference voltage. The second MOS transistor and the second capacitor are connected between the second crystal terminal and the reference voltage. The gates of both MOS transistors are connected to the output node of the pre-amplifier block. The first and second MOS transistors connect the first and second capacitors to the first and second terminals of the gain stage for a portion of the time responsive to the input tuning voltage.

Abstract: A circuit with a phase-locked loop circuit which generates audio clock signals with zero ppm error from reference clock signals at a reference frequency is presented. The phase-locked loop (PLL) circuit has a first programmable divider circuit connected to the circuit input terminal, a first fixed divider circuit connected to the PLL output terminal and a second programmable divider circuit connected to the first fixed divider circuit, among other elements. The circuit also has several second fixed divider circuits, each second fixed divider circuit connected to the PLL output terminal, and a multiplexer selectively connecting the second fixed divider circuits to the circuit output terminal responsive to a programmable control signal. By properly selecting the integer divisors for the fixed and programmable divisors, the circuit can generate clock signals at any one of the audio sampling frequencies from a video clock signal.

Abstract: A voltage-controlled crystal oscillator circuit with an extended range is presented. The circuit has a crystal oscillator circuit, a phase-locked loop (PLL), and a look-up table. The crystal oscillator circuit generates a signal having a frequency f.sub.ref at its output node responsive to a voltage at its input terminal. The PLL has its input node connected to the crystal oscillator output node and generates a signal at the PLL output node having a frequency f.sub.o. A first divider circuit of the PLL divides the f.sub.ref frequency by a first variable integer M and a second PLL divider circuit divides the f.sub.o frequency by a second variable integer N. The look-up table, which has comparators connected to the input terminal, a counter connected to the comparators and a memory responsive to the counter and storing M and N values, varies M and N responsive to the input terminal voltage so that the voltage-controlled crystal oscillator circuit has an increased frequency range.

Abstract: A high speed divider circuit is provided for phase-locked loops (PLLs). The divider circuit in the feedback loop of the PLL has two divider circuits, a prescalar divide-by-4 circuit, which receives the high frequency signal from the voltage-controlled oscillator (VCO) of the PLL, and a programmable divide-by-N circuit, which resets itself after counting up to N. Responsive to the reset signal from the divide-by-N circuit, the prescalar divider circuit divides the VCO signal by 4+P, where P is a programmable value. This programmable periodic change in the divisor of the prescalar divide circuit allows the divisor in the classic PLL frequency synthesis equation to be set to nearly any number so that the synthesized output frequency of the PLL can be set with very fine resolution.