Abstract: A method of producing a multi-level electronic device that begins with machining into a sheet of dielectric material from a surface to create a set of first indentations at a first level. Conductive material is then deposited into the first indentations to create a set of first conductive features. The first indentations are then substantially filled with dielectric material. The process is continued by machining again into the sheet of dielectric material from a surface and thereby creating a set of second indentations at a second level. Further conductive material is deposited into the second indentations to create a set of second conductive features.

Abstract: A method of constructing a multilayer electric apparatus, comprising the steps of first providing a set of dielectric layers and forming a set of conductive features and at least one fiducial marking, in mutual reference to each other, on a first one of the dielectric layers. Next, the dielectric layers are joined together to form a stack, such that the first of the dielectric layers is interposed depthwise between others of the dielectric layers and the at least one fiducial marking is distinctly observable from outside of the stack. Finally, a via is drilled from the exterior of the stack to one of the conductive features of the first dielectric layer, referencing the drilling to the fiducial marking.

Abstract: A method of constructing an electric apparatus, comprising the following steps. First, a set of dielectric layers is provided. Next, a set of conductive features and at least one fiducial marking are formed on a first one of the dielectric layers, in mutual reference to each other so that their relative positions are known to a first tolerance. Then, a set of pin holes is formed in each dielectric layer, each pin hole formed in relation to the fiducial marking for its dielectric layer and all of the sets of pin holes having a mutually identical placement. Finally the dielectric layers are arranged onto a pin fixture having a set of pins that match the mutually identical placement of the pin holes.

Abstract: A method of constructing a planar array of electrical contact pads is disclosed, comprising the following steps. First, providing a set of dielectric layers each having two major surfaces and forming a set of first conductive paths on a first major surface, the paths terminating at or before an interior perimeter, to leave an interior area within the interior perimeter free of conductive paths and an exterior area outside of the interior perimeter having the first conductive paths. Second, forming a set of second conductive paths on a second major surface, the second conductive paths terminating generally inside the interior perimeter. Third, joining the sets of dielectric layers to form a depthwise stack of layers, the stack of layers having a top surface and the first major surface being interposed depthwise between the top surface and the second major surface.