Abstract: An electronic watch circuit for controlling the operation of a watch having analogue hands has an integrated circuit which contains data values to be transmitted to registers and transmitted to peripheral members of the watch. The electronic watch circuit further has a quartz crystal providing the clock base frequency to the integrated circuit and a connecting device arranged for enabling the peripheral member controllers, the quartz crystal, and the processor to communicate data relating to the operation of the watch to each other. The electronic circuit further has a microcontroller including a processor connected to a programmable memory. The integrated circuit has an interface, the microcontroller has a further interface, and the microcontroller is connected with integrated circuit by the interfaces allowing bidirectional exchange of data between the microcontroller and the integrated circuit.

Abstract: A device (10) to detect and measure static electric charge (q) on an object (100) being positioned in a distance (r.) from an input electrode (11) of the device (10) comprises at least one MOS field transistor (20). The input electrode (11) is connected with the gate electrode (21) of the MOS-FET (20) to detect said electrical charge. The MOS-FET (20) can comprise a gate oxide layer underneath the gate (21) and over the source (22) and drain (23) areas having a sufficient thickness to allow the MOS field transistor (20) to withstand several kilovolts (kV) of voltage and to avoid the loss of charges by tunnel effect due to the high potential of the gate electrode during ESD events.

Abstract: A device (10) to detect and measure static electric charge (q) on an object (100) being positioned in a distance (r.) from an input electrode (11) of the device (10) comprises at least one MOS field transistor (20). The input electrode (11) is connected with the gate electrode (21) of the MOS-FET (20) to detect said electrical charge. The MOS-FET (20) can comprise a gate oxide layer underneath the gate (21) and over the source (22) and drain (23) areas having a sufficient thickness to allow the MOS field transistor (20) to withstand several kilovolts (kV) of voltage and to avoid the loss of charges by tunnel effect due to the high potential of the gate electrode during ESD events.