Abstract: A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions nearly as an ideal pass gate in cryogenic cross-bar applications.

Abstract: A method for determining sequential hardware equivalence between two designs and whether one design can replace another design is disclosed whereby the designs are compared utilizing OBDD representations of the designs. The set of states in each of the designs that are equivalent to each other, equivalent-state-pairs, is first determined and it is then determined whether there exists a sequence of inputs that can take all states pairs to the equivalent-state-pair set. This results in a declaration of equivalence in the two designs. An essential reset sequence is then determined, which is then represented by the sequence of inputs to move the designs to a reset state. This, therefore, gives an essential reset sequence for the design and also gives the essential reset states for the design. The essential reset states of the design can then be compared to all states of the designs and, if they are equal, the design is replaceable.

Abstract: A scalable visualization system includes a plurality of scalable tiles (10) that each comprise a display portion (18) and a processing portion (20). Each of the display portions (18) define a portion of a physical display space. Each of the processing sections defines a processing node in the parallel processing system. The parallel processing system operating on a single node or a plurality of nodes. A message fabric (36) is provided to connect CPU nodes (34) and each of the tiles (10) together. The tiles (10) are scaled by interconnecting them to form the desired display space with each of the display elements (18). As each tile (10) is added to the overall display space, an additional CPU node (34) is also added, such that not only is the display space scaled up from a physical coordinant standpoint, but the processing power is also scaled up. In addition, each of the CPU nodes (34) is operable to update an associated display list (28) that defines the parameters of the display element (18 ).

Abstract: A substrate for attaching electrical devices having an interconnect wiring structure and a support for the interconnect, the support having a number of vias, or throughholes, extending therethrough and electrically connected to the interconnect. The substrate allows for attachment of the electrical devices on the side of the support opposite the interconnect at the vias, rather than on the interconnect itself. By so doing, the chips can be packed more density since the area between the chips normally reserved for engineering change pads, test pads and the like is not required, these functions being performed on the interconnect on the opposite side of the substrate.

Abstract: A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions as a nearly ideal pass gate in cryogenic applications.