Abstract: A memory array area and a periphery circuit region on the surface of a semiconductor wafer are defined, and a gate oxide layer and an undoped polysilicon layer are sequentially formed on the wafer. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer, followed by etching of the doped polysilicon layer in the memory array area down to a predetermined thickness. Next, a silicide layer and a protection layer are formed on the surface of the semiconductor wafer. A photo-etching-process (PEP) is used to etch portions of the protection layer, the silicide layer, the undoped polysilicon layer and the doped polysilicon layer to form a plurality of gates. Finally, a LDD and spacers of each MOS transistor, and a source and a drain of each MOS transistor in the periphery circuit region are formed.