Abstract: A linear charger includes a constant current charging circuit and a thermal regulation circuit. The constant current charging circuit is arranged to generate a charging current, and includes a first transconductance amplifier, wherein the first transconductance amplifier has a positive terminal, a negative terminal, and an output terminal. The thermal regulation circuit is coupled to the output terminal and the negative terminal of the first transconductance amplifier, and is arranged to generate and modulate a thermal regulation current and an amplifier reference voltage with temperature, and transmit the thermal regulation current and the amplifier reference voltage to the output terminal and the negative terminal of the first transconductance amplifier, respectively.

Abstract: A method for estimating a rotor angle and a rotor speed of a permanent magnet synchronous motor (PMSM) includes: receiving a d-axis voltage driving signal of the PMSM, and obtaining a first estimated rotor speed of the PMSM according to the d-axis voltage driving signal; receiving a speed command, and obtaining a second estimated rotor speed of the PMSM according to the speed command; performing a weighting adjustment operation upon the first estimated rotor speed and the second estimated rotor speed to obtain a third estimated rotor speed for estimating the rotor speed of the PMSM; and performing an integration operation upon the third estimated rotor speed to obtain an estimated rotor angle for estimating the rotor angle of the PMSM.

Abstract: A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.

Abstract: An audio amplifier with duty ratio control is provided. The audio amplifier comprises a pulse width modulation modulator, a power stage, and a voltage converter. The pulse width modulation modulator is configured to receive an input signal for generating a pulse width modulation signal. The power stage is configured to output an output signal according to a supply voltage and the pulse width modulation signal. The voltage converter is configured to adjust voltage level of the supply voltage according to the pulse width modulation signal. The audio amplifier is configured to adjust the voltage level of the supply voltage when duty ratio of the pulse width modulation signal is greater than a duty ratio threshold.

Abstract: A control method applied to a servomotor, wherein the servomotor includes a motor, and the control method includes: setting a mode of the servomotor as a predetermined mode corresponding to a predetermined communication protocol; receiving an input signal from a controller for controlling the motor, wherein the controller is coupled to the servomotor; and switching the mode of the servomotor from the predetermined mode to one of a plurality of candidate modes according to a frequency of the input signal.

Abstract: A control circuit for controlling a DC-DC converter is provided. The control circuit comprises a first sensor, second sensor, error amplifier, signal conditioning circuit, first comparison circuit, second comparison circuit, and driver circuit. The error amplifier is configured to receive a feedback voltage and a reference voltage for generating a first voltage. The signal conditioning circuit is configured to receive the first voltage for generating a second voltage and a third voltage. The first comparison circuit is configured to make a comparison based on a first sensing signal from the first sensor and the second voltage for generating a first comparison signal. The second comparison circuit is configured to make a comparison based on a second sensing signal from the second sensor and the third voltage for generating a second comparison signal. The driver circuit is for driving a power stage according to the first and second comparison signals.

Abstract: A control circuit for adaptive noise margin control for a constant on time (COT) converter comprises an input reference terminal, amplifier, first switch device, voltage divider, trigger circuit, and output reference terminal. The amplifier has an input terminal coupled to the input reference terminal receiving a reference voltage signal. The first switch device has a control terminal coupled to an output of the amplifier, a first conduction terminal for receiving a voltage source signal, and a second conduction terminal. The voltage divider is coupled to the second conduction terminal and another input terminal of the amplifier. The trigger circuit, coupled to the voltage divider, is for triggering voltage change of a modified reference voltage signal selectively according to a high-side control signal of the COT converter. The output reference terminal coupled to the second conduction terminal outputs the modified reference voltage signal.

Abstract: An audio amplifier includes a plurality of power stages, a driving circuit, and a power stage control circuit. The driving circuit is arranged to drive the power stages. The power stage control circuit includes a feedback circuit and a control circuit. The feedback circuit is coupled to the power stages, and is arranged to generate a feedback signal according to at least one detection input, wherein the at least one detection input includes at least one of a power, a voltage signal corresponding to a switching time of the power stages, and a voltage signal corresponding to a switching frequency of the power stages. The control circuit is coupled between the feedback circuit and the power stages, and is arranged to generate a control signal according to the feedback signal, wherein the control signal is arranged to dynamically control a number of turned-on power stages in the power stages.

Abstract: A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.

Abstract: Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.

Abstract: An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.

Abstract: A semiconductor device with contact check circuitry is provided. The semiconductor device includes a plurality of pads, an internal circuit, and a contact check circuit. The plurality of pads includes a first pad and a second pad. The internal circuit is coupled to the plurality of pads. The contact check circuit, at least coupled to the first pad and the second pad, is used for checking, when the semiconductor device is under test, contact connections to the first pad and the second pad to generate a check result signal according to comparison of a first test signal and a second test signal received from the first pad and the second pad with at least one reference signal.

Abstract: An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.

Abstract: An integrated circuit die forming method, for forming a plurality of integrated circuit dies on a semiconductor wafer, comprising: forming a first device, a second device in a first die in a first area; forming a metal layer connected to the first device and the second device; forming a third device, a fourth device in a second die in a second area; forming the metal layer connected to the third device and the fourth device, wherein a scribe area exists between the first area and the second area is separated by; wherein the first device and the third device are used for synchronization and are components of a class D amplifier; wherein the second device is used for preventing leakage currents of the first die and the fourth device is used for preventing leakage currents of the second die.

Abstract: A method for determining an initial rotor position of a permanent magnet synchronous motor (PMSM) includes: generating a plurality of transient currents by applying a plurality of voltages to each phase stator winding of a three phase stator winding of the PMSM; generating three phase current differences according to the plurality of transient currents; determining a first zone in which the initial rotor position of the PMSM is located according to the three phase current differences, wherein angles between 0-360 degrees are divided into a plurality of zones, and the first zone is selected from the plurality of zones; calculating three line current differences according to the three phase current differences; and determining the initial rotor position of the PMSM according to the first zone and the three line current differences.

Abstract: A method for increasing a resolution by N bits performed by a processing circuit of a motor driving system, where N is a positive integer, and the method includes: performing a conversion upon an analog command, to generate a command count value; performing a first N-bit right-shifting operation upon the command count value, to generate an initial output value; performing a logical operation upon the command count value, to generate a low bit value; generating an overflow value according to the low bit value; and determining a final output value according to the initial output value and the overflow value.

Abstract: A constant on time converter control circuit and a constant on time converter are provided. The constant on time converter control circuit comprises an error amplifier, a voltage to current converter, and an initial current source. The error amplifier is for receiving a reference voltage signal and a feedback voltage signal and outputting a compensated voltage signal. The voltage to current converter receives the compensated voltage signal and outputs a converted current signal. The initial current source provides an initial current signal. The initial current signal and the converted current signal form a new reference voltage signal. A constant on time OFF time comparator receives the new reference voltage signal and the feedback voltage signal and outputs a control signal. The control signal affects the turning on and turning off of electronic switches to produce an output voltage of a constant on time converter.

Abstract: A leveling equalizer includes a graphic equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a gain control circuit. The graphic equalizer circuit processes a first input signal and output a first output signal and a second output signal. The first multiplication circuit multiplies the first output signal and one of an adjustable gain value and a fixed gain value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and another of the adjustable gain value and the fixed gain value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The gain control circuit dynamically adjusts the adjustable gain value according to the equalizer output signal.

Abstract: A control circuit arranged to detect an initial rotor position of a brushless DC motor includes: a voltage integrator circuit, arranged to perform integration upon an input voltage, to generate a plurality of integrated voltages; a PWM generating circuit, arranged to generate and output a plurality of PWM signals to the brushless DC motor through a drive circuit, and stop outputting a PWM signal that is any of the plurality of PWM signals to the brushless DC motor according to an integrated voltage corresponding to the PWM signal; a current receiving circuit, arranged to receive a plurality of feedback currents from the brushless DC motor; a comparison circuit, arranged to perform comparison upon the plurality of feedback currents, to generate a comparison result; and a decision circuit, arranged to detect the initial rotor position according to the comparison result.

Abstract: A digital buffer device with self-calibration includes a first buffer circuit, detection circuit, and calibration circuit. The first buffer circuit has a buffer input terminal for receiving an input signal and a buffer output terminal as output of the digital buffer device. The detection circuit includes at least one second buffer circuit for receiving at least one reference signal and generating at least one detection signal to indicate circuit characteristic variations of the at least one second buffer circuit. The at least one second buffer circuit is of a same type of buffer as the first buffer circuit. The calibration circuit has a calibration input terminal for receiving the input signal, and a calibration output terminal coupled to the buffer output terminal. The calibration circuit is for calibrating the first buffer circuit to generate an output signal according to the input signal and the at least one detection signal.