Patents Assigned to Microelectronics Technology Inc.
  • Patent number: 5654245
    Abstract: The invention provides a method and structure in which a nucleating species [54] is implanted through apertures [52] of a metal-phobic layer [40] into a support layer [17] and copper or a like metal is selectively grown at the implant site or sites. The implant support layer [17] is preferably composed of a material which inhibits diffusion therethrough of the copper or other like grown metal.
    Type: Grant
    Filed: March 23, 1993
    Date of Patent: August 5, 1997
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Gregory Lee Allen
  • Patent number: 5608252
    Abstract: Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the Latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.
    Type: Grant
    Filed: December 15, 1994
    Date of Patent: March 4, 1997
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Tatsuo Nakato
  • Patent number: 5585768
    Abstract: The present invention discloses an electromagnetic wave transmission device comprising separately installed metal pins and a printed pin on a printed circuit board. The device is used to receive vertical and horizontal signals; by adjusting the positions of the internal constituent components, the objective of improving signal isolation is achieved. Under a different implementation of the present invention, the degree of isolation is improved by using a metal rod to replace a printed wire connection.
    Type: Grant
    Filed: July 12, 1995
    Date of Patent: December 17, 1996
    Assignee: Microelectronics Technology Inc.
    Inventor: Shih-Kuei Wei
  • Patent number: 5552563
    Abstract: A modified lead frame is provided for use with electrical component test handlers. A conventional multiple-parallel-conductor lead frame is modified to include two broad, electrically conductive shields positioned on opposite sides of the lead frame. Each shield covers a major portion of one side of the lead frame. Such lead frames are designed for mounting in a predetermined orientation on a lead frame holder, with one side facing toward, and the other side facing away from, the major mass of the holder. The conductive shield positioned on the side facing away from the holder on the modified lead frame of the present invention is electrically coupled to one or more selected conductors on the lead frame. The one or more selected conductors include the power or ground conductor which supplies power to a test component during tests. The shield which faces toward the holder is electrically isolated from all the conductors on the lead frame by an intermediate insulating layer.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: September 3, 1996
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki
    Inventors: Jeff E. Conder, Meral B. Woodberry
  • Patent number: 5545512
    Abstract: The invention provides an improved planarizing methodology for forming high-definition photolithographic masks of the type used in semiconductor integrated circuit manufacturing. A layer of planarizing photoresist is first applied to the surface topography of a semiconductor wafer substrate and shallow-penetrating radiation is then used to irradiate the surface of the photoresist. The radiation creates a blanket irradiated layer, adjacent the surface of the resist, consisting of an acid and resist in solution. The acid/resist solution readily absorbs and incorporates silicon. Next, the wafer is exposed to a silicon-containing compound, or softbaked in a silicon-containing environment, creating a silicon-enriched region adjacent the surface of the photoresist. An imaging resist is then applied to the resist, and a photolithographic mask is formed in the imaging resist. An etching step transfers the mask to the silicon-enriched region of the photoresist.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: August 13, 1996
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Tatsuo Nakato
  • Patent number: 5537100
    Abstract: A pager decoding system is provided which is compatible with the POCSAG encoding standard and which improves battery savings. The disclosed pager includes a baud rate detector for evaluating incoming transmissions to determined if the baud rate is compatible with the decoder, and a preamble detector for determining if preamble code is being transmitted. Baud rate information and preamble code information are sampled frequently when the pager's radio receiver is tuned on, to evaluate whether a valid transmission is being received and whether the pager's internal clock is synchronized with the transmission. In the methodology of the invention, when the pager is on standby and waiting to receive a transmission the radio receiver is periodically energized to search for valid data having the correct baud rate, and to search for POCSAG preamble code. Signals with the incorrect baud rate are quickly detected and the radio circuit is shut off to save battery power.
    Type: Grant
    Filed: April 6, 1994
    Date of Patent: July 16, 1996
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Bryan S. Hallberg
  • Patent number: 5514897
    Abstract: A graduated concentration profile is used for defining a buried isolation region in a semiconductor device. Smaller concentrations of dielectric-defining particles are used for implantation at the deepest levels of the isolation region in order to reduce the defect density in an overlying epi layer.
    Type: Grant
    Filed: November 10, 1994
    Date of Patent: May 7, 1996
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Tatsuo Nakato
  • Patent number: 5502674
    Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.
    Type: Grant
    Filed: April 6, 1994
    Date of Patent: March 26, 1996
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventors: Michael J. Griffus, Robert G. Pollachek, Giao N. Pham
  • Patent number: 5473556
    Abstract: A digit reversing system is disclosed for handling mixed radix FFT operations with arbitrary arrangements of radices. In a first step, all bits in an integer field of size log.sub.2 N are position reversed. In a second step, subfields of the output produced in the first step are individually unreversed at the local level to produce unreversed digits. The output is used for appropriately arranging input terms applied to a mixed-radix multi-stage Fast Fourier Transform (FFT) process.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: December 5, 1995
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventors: Raul A. Aguilar, Jeffrey L. Miller
  • Patent number: 5468657
    Abstract: A method is provided for improving the electrical isolation between surface regions and underlying support regions in SIMOX buried oxide wafers. The method implants nitrogen ions into a wafer to approximately the same depth as oxygen ions are implanted during SIMOX processing. A subsequent heating step causes the nitrogen ions to migrate to the interface region between the buried oxide and the upper and lower semiconductor regions of the substrate. The nitrogen passivates the interface regions to reduce the presence of buried free electrons trapped in the substrate. Nitrogen implantation can be performed before, during, or after the oxygen is implanted. Nitrogen ions can also be implanted after the SIMOX buried silicon dioxide layer has been formed. If the latter alternative is followed, the wafer must be subsequently heated to migrate the nitrogen ions to the interface regions within the substrate. Such subsequent heating can be performed as part of the formation of devices on the substrate.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: November 21, 1995
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Sheng T. Hsu
  • Patent number: 5448706
    Abstract: A one-chip address generator for producing a sequence of address signals for application to a memory containing a plurality of circular buffers. The address generator chip is capable of processing service requests from a plurality of channels on a prioritized basis. Service requests can arrive asynchronously at different rates. A channel-specific length or overlap value can be assigned to each servicing of a request. A seamless pipeline structure is provided for processing the service requests of subsequent channels immediately after completion of service for a first requesting channel.
    Type: Grant
    Filed: May 13, 1992
    Date of Patent: September 5, 1995
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventors: Michael E. Fleming, Eric C. Anderson
  • Patent number: 5439848
    Abstract: A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer [233]; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer [233]; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor [223] extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: August 8, 1995
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventors: Sheng T. Hsu, Robert G. Pollachek
  • Patent number: 5436175
    Abstract: The invention provides a method of forming shallow SIMOX (Separation by IMplantation of OXygen) substrates by implantation of molecular oxygen ions (O.sub.2 +), instead of implanting atomic oxygen ions (O+) as is done in prior art SIMOX processes. Use of molecular oxygen ions (O.sub.2 +) doubles the yield of oxygen atoms implanted for each unit of electric charge deposited in the wafer. The resultant structure, after annealing, has a defect density which is not substantially different from SIMOX processing using atomic oxygen ions (O+). An alternative method for implanting molecular nitrogen ions is also disclosed.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: July 25, 1995
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventors: Tatsuo Nakato, Narayanan Meyyappan
  • Patent number: 5430318
    Abstract: A BiCMOS structure in which the bipolar transistor is preferably arranged vertically and the MOS transistors are formed on insulator. SIMOX techniques may be used to form a starting substrate.
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: July 4, 1995
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Sheng T. Hsu
  • Patent number: 5429987
    Abstract: A method for forming interconnects in an integrated circuit chip which includes a plurality of active devices over which a layer of dielectric material is deposited. The method comprises: (a) depositing a selective nucleating layer on the dielectric layer; (b) depositing a sacrificial layer over the nucleating layer; (c) pattering the sacrificial layer and nucleating layer such that the resulting pattern of the nucleating layer and sacrificial layer is equivalent to the desired pattern of conductive lines; (d) depositing a sidewall guide material over the patterned sacrificial and nucleating layers; (e) forming sidewall guides; (f) removing the sacrificial layer; and (g) depositing conductive material between the sidewall guides and on the nucleating layer. The nucleating layer may comprise titanium nitride, the sacrificial layer may comprise silicon dioxide, the sidewall guide material may comprise silicon nitride, and the conductive material may comprise copper.
    Type: Grant
    Filed: January 25, 1993
    Date of Patent: July 4, 1995
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Gregory L. Allen
  • Patent number: 5403685
    Abstract: Sub-micron features are defined photo-lithographically by combining phase-shifting techniques with conventional photo lithographic techniques. In a first step, phase-shifting edges are defined in a photoresist layer. Dark-bands develop at the phase-shifting edges due to wavefront interference of an illuminating radiation in a subsequent exposure step. Development leaves behind sub-micron sections of photoresist which were covered by the dark-band regions. The dark-band sections are hardened and overcoated with a new layer of photoresist. A second pattern is projected onto the second layer of photoresist using conventional techniques. The second pattern is developed so as to create features having dimensions reduced by parts of the dark-band sections previously developed.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: April 4, 1995
    Assignees: Sharp Kabushiki Kaisha, Sharp Microelectronics Technology, Inc.
    Inventors: David A. Vidusek, Hiroki Tabuchi
  • Patent number: 5395771
    Abstract: A graduated concentration profile is used defining a buried isolation region in a semiconductor device. Smaller concentrations of dielectric-defining particles are used for implantation at the deepest levels of the isolation region in order to reduce the defect density in an overlying epi layer.
    Type: Grant
    Filed: April 25, 1994
    Date of Patent: March 7, 1995
    Assignees: Sharp Kabushiki Kaisha, Sharp Microelectronics Technology, Inc.
    Inventor: Tatsuo Nakato
  • Patent number: 5370969
    Abstract: The invention provides a trilayer structure and photolithographic method which permits use of high-resolution optics with a relatively small depth of focus for patterning a substrate. A trilayer lithographic structure in accordance with the invention comprises: (a) an out-gas resistant planarization layer deposited on a substrate; (b) a chemical-vapor-deposited interfacial film formed on the planarization layer; and (c) a photosensitive resist layer of a thickness equal to or less than one micron deposited on the interfacial film. A method in accordance with the invention comprises the steps of: (a) depositing an out-gas resistant planarization layer on a substrate; (b) chemical-vapor-depositing an interfacial film on the planarization layer; and (c) forming a photosensitive resist layer of a thickness equal to or less than one micron on the interfacial film.
    Type: Grant
    Filed: July 28, 1992
    Date of Patent: December 6, 1994
    Assignees: Sharp Kabushiki Kaisha, Sharp Microelectronics Technology, Inc.
    Inventor: David A. Vidusek
  • Patent number: 5323353
    Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: June 21, 1994
    Assignees: Sharp Microelectronics Technology Inc., Sharp Kabushiki Kaisha
    Inventors: Michael J. Griffus, Robert G. Pollachek, Giao N. Pham
  • Patent number: D360621
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: July 25, 1995
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventor: Mark Schoening