Patents Assigned to Microlink Devices, Inc.
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Patent number: 9356162Abstract: The present application utilizes an oxidation process to fabricating a Group III-V compound semiconductor solar cell device. By the oxidation process, a window layer disposed on a cell unit is oxidized to enhance the efficiency of the solar cell device. The oxidized window has an increased band gap to minimize the surface recombination of electrons and holes. The oxidized window also improves transparency at the wavelengths that were absorbed in the conventional window layer.Type: GrantFiled: January 28, 2010Date of Patent: May 31, 2016Assignee: MicroLink Devices, Inc.Inventors: Noren Pan, Christopher Youtsey, David S. McCallum, Victor C. Elarde, John M. Dallesasse
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Patent number: 8993366Abstract: The method of the invention includes the sequential steps of providing a plurality of solar cells, interconnecting the solar cells using one or more interconnect tabs, attaching the interconnect tabs to a top side of the solar cell to interconnect the plurality of solar cells by coupling an exposed top surface of a first solar cell to a top surface of an adjacent second solar cell, attaching one or more bypass diodes to a top side of the solar cell, then next applying an adhesive to a first film layer, placing the plurality of solar cells onto the first film layer, then next applying an adhesive to a second film layer, placing the plurality of solar cells and first film layer onto the second film layer to form a sheet assembly, and then forming the solar sheet from the sheet assembly.Type: GrantFiled: June 28, 2013Date of Patent: March 31, 2015Assignee: MicroLink Devices, Inc.Inventors: Raymond Chan, Haruki Miyamoto
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Patent number: 8993873Abstract: A solar cell structure is provided for reducing shadow losses without increasing series resistance in the solar cell device. The solar cell device may form an electrical contact to a solar cell emitter layer from the backside of the solar cell device. With this structure, the emitter contact shadow losses may be reduced significantly while simultaneously decreasing device series resistance.Type: GrantFiled: November 25, 2009Date of Patent: March 31, 2015Assignee: MicroLink Devices, Inc.Inventors: Christopher Youtsey, Francis Tuminello, Victor C. Elarde
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Patent number: 8912631Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.Type: GrantFiled: March 1, 2011Date of Patent: December 16, 2014Assignee: MicroLink Devices, Inc.Inventors: Noren Pan, Andree Wibowo
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Patent number: 8450162Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.Type: GrantFiled: April 5, 2011Date of Patent: May 28, 2013Assignee: MicroLink Devices, Inc.Inventors: Noren Pan, Andree Wibowo
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Patent number: 8440492Abstract: An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.Type: GrantFiled: October 11, 2012Date of Patent: May 14, 2013Assignee: MicroLink Devices, Inc.Inventors: Raymond Chan, Christopher Youtsey
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Patent number: 8426237Abstract: An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.Type: GrantFiled: October 11, 2012Date of Patent: April 23, 2013Assignee: MicroLink Devices, Inc.Inventors: Raymond Chan, Christopher Youtsey
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Patent number: 8361827Abstract: An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.Type: GrantFiled: May 4, 2010Date of Patent: January 29, 2013Assignee: MicroLink Devices, Inc.Inventors: Raymond Chan, Christopher Youtsey
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Publication number: 20120088374Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.Type: ApplicationFiled: April 5, 2011Publication date: April 12, 2012Applicant: MicroLink Devices, Inc.Inventors: Noren Pan, Andree Wibowo
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Patent number: 7994419Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.Type: GrantFiled: July 3, 2008Date of Patent: August 9, 2011Assignee: MicroLink Devices, Inc.Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum, Genevieve Martin
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Patent number: 7923318Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.Type: GrantFiled: February 7, 2008Date of Patent: April 12, 2011Assignee: MicroLink Devices, Inc.Inventors: Noren Pan, Andree Wibowo
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Publication number: 20100237388Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.Type: ApplicationFiled: March 25, 2010Publication date: September 23, 2010Applicant: MicroLink Devices, Inc.Inventors: Noren PAN, Andree Wibowo
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Patent number: 7687886Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.Type: GrantFiled: June 14, 2005Date of Patent: March 30, 2010Assignee: MicroLink Devices, Inc.Inventors: Noren Pan, Andree Wibowo
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Publication number: 20090044860Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.Type: ApplicationFiled: July 3, 2008Publication date: February 19, 2009Applicant: MicroLink Devices, Inc.Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum
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Publication number: 20090038678Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.Type: ApplicationFiled: July 3, 2008Publication date: February 12, 2009Applicant: MicroLink Devices, Inc.Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum
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Publication number: 20080230806Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.Type: ApplicationFiled: February 7, 2008Publication date: September 25, 2008Applicant: MicroLink Devices, Inc.Inventors: Noren Pan, Andree Wibowo
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Publication number: 20060049485Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.Type: ApplicationFiled: June 14, 2005Publication date: March 9, 2006Applicant: MicroLink Devices, Inc.Inventors: Noren Pan, Andree Wibowo
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Patent number: 6917061Abstract: A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer allow the heterojunction bipolar transistor to realize a lower turn-on voltage threshold. The thickness of the emitter layer if utilized is kept to a minimum to reduce the associated space charge recombination current in the heterojunction bipolar transistor.Type: GrantFiled: July 22, 2002Date of Patent: July 12, 2005Assignee: Microlink Devices, Inc.Inventors: Noren Pan, Byung-Kwon Han
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Patent number: 6784450Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a graded base layer formed from antimony. The graded base allows the heterojunction bipolar transistor to establish a quasi-electric field to yield an improved cutoff frequency.Type: GrantFiled: July 22, 2002Date of Patent: August 31, 2004Assignee: MicroLink Devices, Inc.Inventors: Noren Pan, Byung-Kwon Han
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Patent number: 6661037Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a contact region formed from InGaAsSb. The contact region allows an emitter region of the heterojunction bipolar transistor to realize a lower contact resistance value to yield an improved cutoff frequency (fT).Type: GrantFiled: July 22, 2002Date of Patent: December 9, 2003Assignee: MicroLink Devices, Inc.Inventors: Noren Pan, Byung-Kwon Han