Patents Assigned to Microlink Devices, Inc.
  • Patent number: 9356162
    Abstract: The present application utilizes an oxidation process to fabricating a Group III-V compound semiconductor solar cell device. By the oxidation process, a window layer disposed on a cell unit is oxidized to enhance the efficiency of the solar cell device. The oxidized window has an increased band gap to minimize the surface recombination of electrons and holes. The oxidized window also improves transparency at the wavelengths that were absorbed in the conventional window layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: May 31, 2016
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Christopher Youtsey, David S. McCallum, Victor C. Elarde, John M. Dallesasse
  • Patent number: 8993366
    Abstract: The method of the invention includes the sequential steps of providing a plurality of solar cells, interconnecting the solar cells using one or more interconnect tabs, attaching the interconnect tabs to a top side of the solar cell to interconnect the plurality of solar cells by coupling an exposed top surface of a first solar cell to a top surface of an adjacent second solar cell, attaching one or more bypass diodes to a top side of the solar cell, then next applying an adhesive to a first film layer, placing the plurality of solar cells onto the first film layer, then next applying an adhesive to a second film layer, placing the plurality of solar cells and first film layer onto the second film layer to form a sheet assembly, and then forming the solar sheet from the sheet assembly.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 31, 2015
    Assignee: MicroLink Devices, Inc.
    Inventors: Raymond Chan, Haruki Miyamoto
  • Patent number: 8993873
    Abstract: A solar cell structure is provided for reducing shadow losses without increasing series resistance in the solar cell device. The solar cell device may form an electrical contact to a solar cell emitter layer from the backside of the solar cell device. With this structure, the emitter contact shadow losses may be reduced significantly while simultaneously decreasing device series resistance.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: March 31, 2015
    Assignee: MicroLink Devices, Inc.
    Inventors: Christopher Youtsey, Francis Tuminello, Victor C. Elarde
  • Patent number: 8912631
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: December 16, 2014
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Patent number: 8450162
    Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: May 28, 2013
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Patent number: 8440492
    Abstract: An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: May 14, 2013
    Assignee: MicroLink Devices, Inc.
    Inventors: Raymond Chan, Christopher Youtsey
  • Patent number: 8426237
    Abstract: An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: April 23, 2013
    Assignee: MicroLink Devices, Inc.
    Inventors: Raymond Chan, Christopher Youtsey
  • Patent number: 8361827
    Abstract: An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: January 29, 2013
    Assignee: MicroLink Devices, Inc.
    Inventors: Raymond Chan, Christopher Youtsey
  • Publication number: 20120088374
    Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.
    Type: Application
    Filed: April 5, 2011
    Publication date: April 12, 2012
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Patent number: 7994419
    Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 9, 2011
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum, Genevieve Martin
  • Patent number: 7923318
    Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: April 12, 2011
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Publication number: 20100237388
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 23, 2010
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren PAN, Andree Wibowo
  • Patent number: 7687886
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: March 30, 2010
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Publication number: 20090044860
    Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.
    Type: Application
    Filed: July 3, 2008
    Publication date: February 19, 2009
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum
  • Publication number: 20090038678
    Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.
    Type: Application
    Filed: July 3, 2008
    Publication date: February 12, 2009
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Glen Hillier, Duy Phach Vu, Rao Tatavarti, Christopher Youtsey, David McCallum
  • Publication number: 20080230806
    Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.
    Type: Application
    Filed: February 7, 2008
    Publication date: September 25, 2008
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Publication number: 20060049485
    Abstract: A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
    Type: Application
    Filed: June 14, 2005
    Publication date: March 9, 2006
    Applicant: MicroLink Devices, Inc.
    Inventors: Noren Pan, Andree Wibowo
  • Patent number: 6917061
    Abstract: A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer allow the heterojunction bipolar transistor to realize a lower turn-on voltage threshold. The thickness of the emitter layer if utilized is kept to a minimum to reduce the associated space charge recombination current in the heterojunction bipolar transistor.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: July 12, 2005
    Assignee: Microlink Devices, Inc.
    Inventors: Noren Pan, Byung-Kwon Han
  • Patent number: 6784450
    Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a graded base layer formed from antimony. The graded base allows the heterojunction bipolar transistor to establish a quasi-electric field to yield an improved cutoff frequency.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: August 31, 2004
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Byung-Kwon Han
  • Patent number: 6661037
    Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a contact region formed from InGaAsSb. The contact region allows an emitter region of the heterojunction bipolar transistor to realize a lower contact resistance value to yield an improved cutoff frequency (fT).
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: December 9, 2003
    Assignee: MicroLink Devices, Inc.
    Inventors: Noren Pan, Byung-Kwon Han