Abstract: Apparatus and method is disclosed for providing hot-add and hot swap capability to a computer system with a processor, and a memory, connected to a system bus. The apparatus includes a first bus, an adapter card slot, a switchable interface unit and hot-swap hot-add program code means. The first bus is connected to the system bus. The adapter card slot has a first port and a second port. The switchable interface unit includes a primary port and a secondary port. The primary port is connected to the first bus and the secondary port is connected to the first port of the adapter card slot. The switchable interface unit is responsive to a hot-swap hot-add power-down request to disconnect the second port from the first bus. The switchable interface unit is also responsive to a power-up request to reconnect the second port to the first bus.

Abstract: Methods of removing and replacing data processing circuitry are provided comprising removing a network interface module from the computer without powering down the computer and removing an interface card from the network interface module. The further acts of replacing the interface card into the network interface module and replacing the network interface module into the computer without powering down the network computer are also performed in accordance with this method.

Abstract: An apparatus for securing a component in a computer chassis. The apparatus provides a tray that may be made from a resilient material in which the computer component is encased. The computer component is thereby isolated from physical shock applied to the chassis, and sound from the component is dampened from escaping the confines of the apparatus. Embodiments of the tray are particularly constructed to be placed near the top of a tower configuration computer and encased by a cover that keeps the component secured. The cover is removable and therefore allows for ready access to the component.

Abstract: One embodiment of the present invention provides a memory system that allows more than one cycle of memory latency for accesses to a synchronously accessed memory. In this embodiment, the memory system includes a memory with a clocked interface and a corresponding clock input. It also includes an output register for storing data outputted from the memory during a read operation. The output register and the memory are coupled together by a data path, for transferring data between the memory and the output register. In this embodiment, the memory system further includes a clock signal coupled to the clocked interface of the memory. The clock signal feeds through a delay element into a clock input of the output register. This causes the output register to receive a delayed clock signal, thereby providing more than one clock cycle of time for data to be read from the memory and latched in the output register.

Abstract: An interface circuit, which can form part of a memory device or a memory controller, includes a read circuit, a write circuit, and a clocking circuit. The read circuit includes two registers or latches that receive alternate data read from burst EDO or synchronous memory. A multiplexer and read output register provide the data to a CPU or other application. If the memory is burst EDO, then the clocking circuit receives the system clock signal and generates a CAS signal based on positive or negative going edges of the clock signal, depending upon delays inherent in the system in which the present invention is employed. The CAS signal is then used to drive the two read latches. If the memory is synchronous memory, then the clock circuit includes an inverter that inverts the clock signal, and provides the inverted clock signal to the synchronous memory. The inverted clock signal is delayed and then used to drive the two read registers.

Abstract: An interface circuit, which can form part of a memory device or a memory controller, includes a read circuit, a write circuit, and a clocking circuit. The read circuit includes two registers or latches that receive alternate data read from burst EDO or synchronous memory. A multiplexer and read output register provide the data to a CPU or other application. If the memory is burst EDO, then the clocking circuit receives the system clock signal and generates a CAS signal based on positive or negative going edges of the clock signal, depending upon delays inherent in the system in which the present invention is employed. The CAS signal is then used to drive the two read latches. If the memory is synchronous memory, then the clock circuit includes an inverter that inverts the clock signal, and provides the inverted clock signal to the synchronous memory. The inverted clock signal is delayed and then used to drive the two read registers.

Abstract: A bus controller controls access to a computer bus by a plurality of bus requesters. The bus controller activates a priority bus request line on the computer bus regardless of which of plural priority bus agents desires to transmit a transaction on the computer bus. The bus controller receives an I/O request signal from a bus agent and determines whether the priority bus request line is in an active state. If the priority bus request line is not in the active state, then the bus controller activates the priority bus request line in response to the I/O request signal. If the priority bus request line is already in the active state, then the bus controller leaves the priority bus request line in the active state for a time period sufficient to enable the bus agent to transmit a transaction on the computer bus. In addition, the bus controller transmits an I/O grant signal to the bus agent to enable the bus agent to transmit the transaction on the computer bus.

Abstract: A method and apparatus for improved computer system power management is described. A power management controller includes a plurality of device idle timers, each associated with a particular I/O device. Expiration of the device idle timers, and the placing of the associated I/O device into a powered-down state, is controlled by device idle time values programmed into timing registers. The device idle time values are regularly updated as a function of time of day, time of week, etc., to optimize power efficiency. The device idle time values are determined by monitoring and recording the history of I/O device use. Thus, an I/O device may be quickly powered-down during those time periods during which device activity is not expected, whereas the I/O device will be maintained in a powered-up state during those times when device activity is probable. Also included are device activation timers which activate a powered-down computer system or particular I/O device in anticipation of a subsequent system event.

Abstract: An apparatus for testing an IDE controller with random constraints, the apparatus including: an IDE controller module for simulating the IDE controller, wherein the IDE controller includes primary and secondary channels and a host interface; a primary control module, coupled to the host interface, for testing the primary channel; a secondary control module, coupled to the host interface, for testing the secondary channel; and a host request module for arbitrating access to the host interface between the primary and secondary control modules.