Abstract: A method and apparatus for using photoemission to determine the endpoint of a dry etch process. In one embodiment, the endpoint of a dry etch process is determined when the dry etch process is acting on a substrate comprising a layer of a first material overlying a second material. The substrate is illuminated with a beam of monochromatic light. The photon energy of the monochromatic light is greater than the work function of one of the two materials, and less than the work function of the other material. Thus the beam of light is capable of inducing photoemission of electrons in only one of the two materials: the material with a work function less than the photon energy of the beam of light. The electrons emitted by the photoemitting material are collected. The current generated by the collected stream of electrons, the photocurrent, is amplified. A time-series of amplified photocurrent measurements is monitored for changes that correspond to the endpoint of the dry etch process.

Abstract: A method and apparatus for creating second order vibrational modes. The apparatus includes a signal generator, a piezoelectric transducer, a plurality of wave propagating beams and reflecting boards. An electric field applied by the signal generator to the piezoelectric transducer induces a unidirectional vibration of the transducer. The vibration is propagated through the beams and reflected by the reflecting boards in a closed polygonal loop. The final reflection direction is perpendicular to the original vibration. A circular or elliptical vibration of the apparatus results. The circular or elliptical vibrational energy can be imparted to the wire bond of an integrated circuit to add strength to the connection.

Abstract: This invention is a process for fabricating a DRAM capacitor having an annularly-grooved, cup-shaped storage-node plate and a cell plate which covers both inner and outer surfaces of the storage-node plate. A plurality of oxide layers having alternately-varying composition are deposited on top of an in-process DRAM array to form a single sacrificial mold layer. In a preferred embodiment of the invention, ozone TEOS oxide is one of the alternately-varying layers, and plasma-enhanced TEOS oxide is the other. Ozone TEOS oxide etches more rapidly than does plasma-enhanced TEOS oxide, and both types of TEOS oxide are etchable with respect to polycrystalline silicon. Following the deposition of the sacrificial mold layer, the mold layer is patterned and anisotropically etched to form a mold opening in the mold layer. Contact to the storage node of the cell access transistor is made at the bottom of the mold opening.

Abstract: A capacitor and method for forming the capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a temperature adjusted to cause a nucleation of the second polysilicon layer. As a result of the nucleation the second polysilicon layer is altered to resemble hemispherical grains. Next the first and second polysilicon layers are oxidized in an oxygen/phosphine ambient. During the oxidation portions of the first and second polysilicon layers are consumed forming a phosphine rich oxide layer on the surface of the hemispherical grains and in portions of the first polysilicon layer lying between the grains which are reduced in size due to the oxidation. A wet etch is then performed to remove the oxide layer. Phosphorous ions are driven into the hemispherical grains during the oxidation thereby doping the grains.

Abstract: A semiconductor integrated circuit having a decode circuit for selecting selected and non-selected wordlines and having a driver circuit for driving a potential to the non-selected wordlines which is less than the lowest potential to which any digit lines are driven during the operation of the semiconductor integrated circuit.

Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

Abstract: A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row.

Abstract: A method for compensating against wafer edge heat loss during rapid thermal processing includes a semiconductor wafer that is exposed to uniform radiant energy across the entire wafer surface. The wafer is exposed by projecting a radiant energy image onto the edge of said semiconductor wafer while providing radiant energy rays directly to the wafer's surface. The radiant energy image comprises reflecting radiant energy rays that pass through a positionally adjustable object onto the edge of the wafer. The positionally adjustable object is optional and is mounted between an optical lens and a radiant energy source or is mounted between a reflector and each radiant energy source (A second optical lens is optional). The energy rays absorbed at the edge of the wafer contain more heat intensity than do the rays which are absorbed by the inner portion of the wafer, thus producing uniform heat across the entire wafer.

Abstract: This invention is a process for making resistor structures having high stability and reliability characteristics. Process parameters are easily modifiable to adjust the resistivity of the structures. A layer of titanium nitride, which may contain certain impurities such as carbon, is deposited via chemical vapor deposition by pyrolization of an organometallic precursor compound of the formula Ti(NR.sub.2).sub.4 either alone or in the presence of either a nitrogen source (e.g. ammonia or nitrogen gas) or an activated species (which may include a halogen, NH.sub.3, or hydrogen radicals, or combinations thereof). The TiN film is then oxidized to create a structure that demonstrates highly stable, highly reliable resistive characteristics, with bulk resistivity values in giga ohm range. In a preferred embodiment of the invention, a predominantly amorphous titanium carbonitride film is deposited on an insulative substrate in a chemical vapor deposition chamber.

Abstract: An integrated circuit (IC) device comprises towers of bonded gold balls located on each bond pad. The towers allow for early encapsulation of the IC die. The IC can then be tested and attached to tab tape or a printed circuit board without particulate contamination concerns.

Abstract: This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. The focus of this invention is a CMOS manufacturing process flow which permits P-channel source/drain doping subsequent to capacitor formation. A main feature of the process is the deposition and planarization of a thick insulative mold layer subsequent to N-channel device patterning, but prior to P-channel device patterning. In one embodiment of the process, portions of this insulative layer overlying the P-channel transistor regions are removed during the storage-node contact etch.

Abstract: A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and the field oxide region to form a trench. The trench comprises a bottom and a first sidewall consisting of silicon and a second sidewall comprising field oxide. The etching step removes a part of a doped region in the substrate. Next, a blanket nitride layer and a blanket oxide layer is formed over the substrate, and a spacer etch is performed on the nitride and oxide layer leaving nitride and oxide over the first and second sidewalls. The trench bottom is oxidized to form a layer of oxide over the bottom of the trench thereby insulating the trench bottom, and the oxide encroaches under the nitride and oxide on the sidewalls to join with the field oxide.

Abstract: The present invention teaches a method for etching a tungsten silicide (WSi.sub.x) film overlying a polysilicon film in an enclosed chamber during a semiconductor fabrication process, by the steps of: providing a patterned mask overlying the WSi.sub.x film thereby providing exposed portions of the WSi.sub.x film; presenting an etchant chemistry comprising NF.sub.3 and HeO.sub.2 to the exposed portions of the WSi.sub.x film at a temperature ranging from -20.degree. C. to 100.degree. C., thereby etching away the exposed portions of the WSi.sub.x film and simultaneously etching substantially vertical sidewalls in the WSi.sub.x film, the etching continues into the polysilicon film, thereby forming a WSi.sub.x /polysilicon stack having substantially vertical sidewalls.

Abstract: Another aspect of the present invention comprises a method for fabricating columnar supports used for an evacuated display, in which an electrode plate is covered with a layer of material having a depth. The material is used to form the columnar supports, and the depth of the layer represents the height of the columnar supports. The material is selectively irradiated with light energy in a pattern causing the material to harden, thereby forming the columnar supports.

Abstract: The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operation, thus test time can be decreased.

Abstract: A method of forming contact to a semiconductor memory device feature comprises the steps of forming a first oxide layer over a feature such as a semiconductor substrate or a conductive line or plate, then forming a hard mask over the first oxide layer. A first patterned resist layer is formed on the hard mask, then the hard mask is patterned using the first resist layer as a pattern. The first resist layer is removed and a second oxide layer is formed over the hard mask. A second patterned resist layer is formed over the second oxide layer and the second oxide layer is etched using the second resist layer as a pattern while, during a single etch step, the first oxide layer is etched using the hard mask as a pattern, the hard mask functioning as an etch stop.

Abstract: A simple, low-power sense circuit is disclosed that accurately tracks charge transfer between the capacitor of a dynamic random access memory cell and its associated digit line. The circuit, which is preferably located in the peripheral circuitry, employs a model access transistor to charge a pull-up node that is coupled to ground through a capacitor which simulates digit line capacitance. The pull-up node is coupled to the gate of a N-channel field-effect output transistor. When voltage on the node reaches the threshold voltage of the output transistor, the output transistor begins to turn on. The output from the output transistor (in this case, ground potential) is fed back to the gate of a P-channel device which couples the node to V.sub.CC. The P-channel device is used to pull up the node to V.sub.CC rapidly once the trip point (i.e., the threshold voltage) of the N-channel output transistor is reached.

Abstract: The invention is a process for cleaning a chamber after a chemical vapor deposition has been performed therein. A residue formed during the deposition is combined with a reactive species to form a gas containing an organic substance once found in the residue and to form a film on the chamber walls and internal parts. The gas and the film are removed from the chamber. The formation of a polymer byproduct on the chamber walls and other internal parts of the chamber is minimized by the method of the invention.

Abstract: A method and circuit for generating a self-refresh mode signal and a self-refresh cycle signal. The circuit is a dynamic random access memory (DRAM) device having a control array of control cells charged to a potential by a current source and having a monitor circuit for monitoring the potential of the control array. The DRAM comprises a discharge circuit which discharges the potential of the control array in response to the monitor circuit detecting when the potential of the control array has reached a trip point. A counter circuit counts the number of cycles of charge and discharge and generates the self-refresh mode signal after a desired count is reached. The counter circuit continues to count the number of cycles of charge and discharge while in the refresh mode and generates a self-refresh cycle signal each time the counter circuit counts a desired number of counts.

Abstract: A multi-port memory device includes a row-column array, a random access port, a plurality of bidirectional serial access memory (SAM) ports, and a switching network. There is one SAM port for each of a plurality of sets of columns. The switching network selectively couples each SAM port with each set, each set with each other set, and each SAM port with each other SAM port. A video random access memory (VRAM) or a multi-port dynamic random access memory (DRAM) of the present invention provides increased flexibility in smaller die area.