Abstract: Methods, systems, and devices for memory fault notification are described. A memory device may receive a configuration corresponding to a circuit node of the memory device, where the circuit node may be selectively coupled with a set of resistors. The memory device may determine a fault condition and couple the circuit node to at least a first resistor based on determining the fault condition. The memory device may bias the circuit node to a first voltage value that satisfies a voltage threshold based on coupling the circuit node to the first resistor. The memory device may output an indication of a fault state to notify a host device that a fault has been detected.

Abstract: Methods, systems, and devices for dynamic random access memory speed bin compatibility are described. For instance, a device (e.g., a memory device, a host device) may combine a first parameter with a second parameter to generate a third parameter, where the first parameter may be associated with a duration for a clock that is coupled with a memory array to perform a clock cycle and the second parameter may be associated with a timing constraint associated with initiating an access operation for the memory array. The device may determine a latency of a column address strobe based on the third parameter relative to (e.g., satisfying) a threshold value and may access one or more memory cells of the memory array based on the latency of the column address strobe.

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

Abstract: Methods, systems, and devices for power-efficient access line operation for memory are described. A memory device may drive a voltage pulse on a first word line included in a set of word lines that is coupled with a master word line. The memory device may then a voltage pulse on a second word line included in the set of word lines coupled with the master word line. In between driving the voltage pulse on the first word line and driving the voltage pulse on the second word line, the memory device may maintain a voltage on the master word line below a threshold level.

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a method can include receiving a command to perform a precharge operation on a set of memory cells in a memory device. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The method can further include accessing one or more sets of bits in a mode register. The one or more sets of bits in the mode register indicate address locations of the plurality of sets of memory cells to disable the flip on precharge operation. The method can further include performing the precharge operation on the set of memory cells. The flip on precharge operation associated with the precharge operation can be disabled for those sets of the plurality of sets of memory cells whose address locations are in the mode register.

Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for control loop circuitry. An interface circuit can comprise a digital to analog converter (DAC) configured to provide a differential output signal, a first control loop portion configured to receive a gain reference voltage and to output a first bias voltage to the DAC; and a second control loop portion configured to receive a common mode voltage of a differential input signal and to output a second bias voltage to the DAC.

Abstract: A memory device comprises multiple memory dice arranged vertically in a stack of memory dice and at least one thermoelectric die contacting the bulk silicon layer of at least one of the memory dice of the multiple memory dice. Each memory die of the multiple memory dice includes an active circuitry layer that includes memory cells of a memory array and a bulk silicon layer. The thermoelectric die is configured to one or both of reduce heat from the memory die when a current is applied to terminals of the thermoelectric die and generate a voltage at the terminals of the thermoelectric die when heat from the memory die is applied to the thermoelectric die.

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

Abstract: Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage.

Abstract: Apparatuses and methods for error correction based on data characteristics are disclosed. Data characteristics can include importance of the data. Data is received at a memory controller from a host device, and a characteristic of the received data is determined. A level of error correction is selected from a plurality of error correction levels for the received data based on the determined characteristic. The received data and an error correction code are written to a memory. The error correction code is generated based on the selected level of error correction. In some implementations, the characteristic of the received data is determined using a neural network.

Abstract: Apparatuses and methods for determining a channel characteristic are disclosed. The channel characteristic can be a characteristic of a channel between a memory controller and a memory. The channel characteristic is determined at the memory controller relating to logic levels of data written to or read from the memory over the channel, and transceiver settings of a transceiver of the memory controller are modified according to the determined characteristic. The channel characteristic can be determined based on storing a pilot signal at the memory controller, causing the pilot signal to be written to the memory, and comparing a read pilot signal corresponding to the written pilot signal with the stored pilot signal.

Abstract: An example apparatus includes a passgate circuit between first and second nodes, the passgate circuit having a plurality of transistors at least two of which are operatively connected in parallel in a first mode and operatively connected in series in a second mode. The plurality of transistors may include first and second transistors coupled in parallel between the first and second nodes and controlled in common by a first control signal activated in the first mode. The plurality of transistors may further include third and fourth transistors connected in series between the first and second nodes and controlled in common by a second control signal activated in the second mode.

Abstract: Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

Abstract: An example apparatus includes a plurality of pairs of input and output signal lines, a plurality of first delay circuits operatively connected between the plurality of input signal lines and the plurality of output signal lines, and a first selector circuit configured to connect a selected one of the plurality of first delay circuits between a selected one of the plurality of pairs of the input and output signal lines.

Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.

Abstract: A host can determine whether to train an AI accelerator of a memory sub-system. Responsive to determining to train the AI accelerator, the host can determine a training category corresponding to a memory access request. The host can also provide an indication to the memory sub-system that causes training of the AI accelerator to be performed based on the training category.

Abstract: A system includes a plurality of memory dice and a processing device coupled to the plurality of memory dice. The processing device is to determine whether an error correcting code (ECC) check of ECC-protected data read from a die of the plurality of memory dice results in detecting an error. In response to detecting the error from the ECC-protected data, the processing device performs a confirmation check that the error is a result of a defect in the die. In response to the confirmation check confirming the die is defective, the processing device ignores a temperature value from the die when determining whether to trigger a thermal-related operation.

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.