Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.

Abstract: Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

Abstract: A processing device coupled to the memory device can be configured to monitor respective raw bit error rates (RBERs) corresponding to a plurality of groups of memory cells of the memory device. The processing device can also be configured to responsive to determining that an RBER corresponding to a particular group of the plurality of groups of memory cells has met a criteria, adjust a read window budget corresponding to the particular group of memory cells.

Abstract: Methods, systems, and devices for an efficient turnaround policy for a bus are described. A device may include a memory and a bus for communicating with the memory. The device may operate the bus in a first direction, relative to the memory, that is associated with a first type of access command. The device may determine, for the memory, that a quantity of queued access commands of a second type are for one or more banks that have satisfied a timing constraint for activating different rows in a same bank. Based on determining that the quantity of queued access commands of the second type are for one or more banks that have satisfied the timing constraint, the device may operate the bus in a second direction, relative to the memory, that is associated with the second type of access command.

Abstract: Apparatuses, systems, and methods for direct refresh management (DRFM) sampling protection. A memory receives a DRFM address and DRFM sampling command from a controller. The memory also samples addresses into an aggressor register. Responsive to receiving the DRFM address, the memory may prevent addresses which match the DRFM address from being added to the aggressor register for at least a period of time. For example, a protect flag may be activated for the period of time. If the aggressor register already contained an address which matched the DRFM address, it may be removed.

Abstract: Systems and methods that may enable alignment of a receiver enable signal with one or more clocking signals. By aligning the receiver operations with the one or more clocking signals, a likelihood of a false or incorrect data capture may be reduced, which may improve operation of a memory system. Reducing a likelihood of incorrect data capture may increase an accuracy of a distortion correction operation of a decision feedback equalizer (DFE).

Abstract: A memory array comprising laterally-spaced memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The laterally-spaced memory blocks in a lower one of the conductive tiers comprises elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks proximate laterally-outer sides of the laterally-spaced memory blocks. A metal silicide or a metal-germanium compound is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier. The metal of the metal silicide or of the metal-germanium compound is the same as that of the elemental-form metal. Other embodiments, including method, are disclosed.

Abstract: Methods, systems, and devices for improved implicit ordered command handling are described. For instance, a memory device may receive, from a host device, a first command and a second command. The memory device may determine whether a first memory operation associated with the first command and a second memory operation associated with the second command are to be performed in an order relative to each other based on a first time when the first command is received relative to a second time when the second command is received. The memory device may select whether to perform a first memory access procedure or a second memory access procedure based on whether the first memory operation and the second memory operation are a same type of memory operation and on whether the first memory operation and the second memory operation are to be performed in the order relative to each other.

Abstract: Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.

Abstract: A system includes a memory device having a plurality of data blocks and a processing device, the processing device to perform operations identifying an erase operation being performed on a first portion of a plurality of data blocks. The operations further include determining a first rate of performance of the erase operation being performed on the first portion of the plurality of data blocks, identifying a write operation being performed on a second portion of the plurality of data blocks, and determining a second rate of performance of the write operation being performed on the second portion of the plurality of data blocks. The operations further include determining whether the second rate of performance corresponds to the first rate of performance and responsive to the second rate of performance not corresponding to the first rate of performance, adjusting the second rate of performance.

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure.

Abstract: Memory with efficient storage of event log data is disclosed herein. In one embodiment, a memory device includes a non-volatile memory subsystem storing a persistent event log file, and a volatile memory subsystem including a working buffer. The memory device is configured to write newly generated event log data of the memory device to the working buffer. The memory device is further configured to write the newly generated first event log data to a first subregion of the persistent event log file. The first subregion can be one of a plurality of subregions of the persistent event log file, and can correspond to an end of event log data stored to the persistent event log file. The volatile memory subsystem can be positioned inside or outside a controller operably connected to the non-volatile memory subsystem.

Abstract: Methods, systems, and devices for payload validation for a memory system are described. A payload receiver may be a device that includes an array of memory cells configured to store data, and a payload transmitter may be a host of a payload receiver (e.g., a host device) or another device that is in communication with the payload receiver. A payload receiver may be configured to receive an information payload and a signature associated with the information payload. The received signature may be based on the information payload and an identifier of the payload receiver previously provided to the payload transmitter. The payload receiver may generate a signature based on the information payload and the identifier of the payload receiver (e.g., as stored or cached at the payload receiver), and authenticate the information payload based on the received signature and the generated signature.

Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.

Abstract: A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.

Abstract: A memory system includes a memory device and a processing device, operatively coupled to the memory device. The processing device performs operations comprising: identifying one or more mandatory scan wordlines of the memory device and one or more remaining wordlines of the memory device; performing a plurality of scan iterations with respect to a plurality of pages of the memory device, such that performing each scan iteration comprises: identifying, among the remaining wordlines, one or more scheduled scan wordlines of the memory device, scanning a subset of pages of the memory device that are addressable by the mandatory scan wordlines and the scheduled scan wordlines; wherein a combination of a first plurality of pages addressable by the scheduled scan wordlines selected by the plurality of scan iterations and a second plurality of pages addressable by the mandatory wordlines comprises the plurality of pages of the memory device.

Abstract: Exemplary methods, apparatuses, and systems including a device health manager for managing health of a memory device. The device health manager identifies a memory device having a service life. The device health manager receives multiple requests to perform one or more computing operations. The device health manager predicts, using a machine learning model, an adjustment of the service life of the memory device using the health data. The device health manager generates a notification including the adjustment of the service life.

Abstract: Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include an interfacing die and at least one additional die communicatively coupled to each other through an internal bus. The interfacing die may be configured to provide a combined external interface for the coupled dies. For the die-to-die communications, a target die may coordinate transfer of communicated data to the internal interface according to a timing signal generated by a source external to the at least one additional die.

Abstract: Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.

Abstract: Methods, systems, and devices for resuming write operation after suspension are described. A memory system may be configured to determine an upper limit of a threshold voltage of a page of a block at which a performance of a write operation was suspended based at least in part on an indication to resume the performance of the write operation that was previously suspended at a memory system; determine a difference between a first quantity of a first logic state stored in the page and a second quantity of the first logic state associated with an unsuspended write operation based at least in part on determining the upper limit of the threshold voltage; and resume the performance of the write operation based at least in part on determining the difference between the first quantity of the first logic state and the second quantity of the first logic state.