Patents Assigned to Micron Technologies, Inc.
  • PROGRAM AND READ TRIM SETTING
    Publication number: 20150221378
    Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Seiichi Aritome
  • APPARATUSES AND METHODS TO DELAY MEMORY COMMANDS AND CLOCK SIGNALS
    Publication number: 20150221355
    Abstract: An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock signal and further configured to add an intrinsic delay to the command signal or the bank address signal and add a forward path delay greater than the intrinsic delay to the first and second clock signals.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 6, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Huy T. Vo, Yantao Ma
  • Memory Systems and Memory Control Methods
    Publication number: 20150220344
    Abstract: Memory systems and memory control methods are described.
    Type: Application
    Filed: February 4, 2014
    Publication date: August 6, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Umberto Siciliani, Tommaso Vali, Walter Di-Francesco, Violante Moschiano, Andrea Smaniotto
  • METHODS AND APPARATUSES INCLUDING AN ASYMMETRIC ASSIST DEVICE
    Publication number: 20150221347
    Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Randy J. Koval, Hiroyuki Sanda
  • DEVICES, SYSTEMS AND METHODS FOR ELECTROSTATIC FORCE ENHANCED SEMICONDUCTOR BONDING
    Publication number: 20150221540
    Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.
    Type: Application
    Filed: February 5, 2014
    Publication date: August 6, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shu Qin, Ming Zhang
  • METHODS OF OPERATING MEMORY DEVICES
    Publication number: 20150221384
    Abstract: Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.
    Type: Application
    Filed: April 14, 2015
    Publication date: August 6, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Nicholas Hendrickson
  • THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS
    Publication number: 20150221612
    Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jaspreet S. Gandhi, Michel Koopmans
  • DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS
    Publication number: 20150220386
    Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Ronald Yamada, Siamack Nemazie, Jui-Yao Yang
  • Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods
    Patent number: 9099442
    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
  • Semiconductor constructions, methods of forming conductive structures and methods of forming DRAM cells
    Patent number: 9099472
    Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
  • Methods and devices for memory reads with precharged data lines
    Patent number: 9099189
    Abstract: Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage, and selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Method providing an epitaxial growth having a reduction in defects and resulting structure
    Patent number: 9099309
    Abstract: Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: August 4, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Song Guo, Yushi Hu, Roy Meade, Sanh D. Tang, Michael P. Violette, David H. Wells
  • Semiconductor with through-substrate interconnect
    Patent number: 9099457
    Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh
  • Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
    Patent number: 9099539
    Abstract: Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Secure compact flash
    Patent number: 9098440
    Abstract: Methods and apparatus are provided, such as a memory card with a processor and nonvolatile memory coupled thereto. The nonvolatile memory has a secure area configured to store a user password and a serial number in encrypted form. The card is configured to grant access to the secure area when the card receives a password that matches the stored user password and the card is coupled to a system having the serial number.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Petro Estakhri, Ngon Le
  • Apparatus and methods for leakage current reduction in integrated circuits
    Patent number: 9100002
    Abstract: This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Vincent Antoine Laurent
  • Polishing systems and methods for removing conductive material from microelectronic substrates
    Patent number: 9099431
    Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Pitch multiplication spacers and methods of forming the same
    Patent number: 9099314
    Abstract: Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: August 4, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • Packaged integrated circuit devices with through-body conductive vias, and methods of making same
    Patent number: 9099571
    Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Yong Poo Chia
  • Field emission devices and methods for making the same
    Patent number: 9099272
    Abstract: The present disclosure includes field emission device embodiments. The present disclosure also includes method embodiments for forming field emitting devices. One device embodiment includes a housing defining an interior space including a lower portion and an upper portion, a cathode positioned in the lower portion of the housing, a elongate nanostructure coupled to the cathode, an anode positioned in the upper portion of the housing, and a control grid positioned between the elongate nanostructure and the anode to control electron flow between the anode and the elongate nanostructure.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Neal R. Rueger