Abstract: A liquid filter housing formed by an enclosure having a sidewall, a bottom and an open top. The bottom is formed from a support structure coupled to a flat plate. The cover may also be formed from a support structure coupled to a flat plate. A support member may be located between the bottom and a mounting surface. The enclosure has an inlet and an outlet communicating with an interior of the enclosure. The inlet and the outlet may be mounted to the bottom and a feed pipe used to direct the inlet flow proximate to an upper section of the enclosure. The cover may be adapted to close the open top, for example using eyebolts.

Abstract: The present invention employs a clock frequency detector in a SDRAM that detects whether an input clock signal is operating at a fast rate (e.g., 125 MHz or a 8 nanosecond access time), or at a slower rate. In response to the input clock frequency, the clock frequency detector outputs a selection signal to control logic circuitry in the SDRAM indicating whether the SDRAM should operate in either a fast or slow mode. The clock frequency detector employs a frequency detector that detects the frequency of the input clock signal. Based on the frequency of the input clock signal, a selector circuit outputs either a fast or slow selection signal to the control logic circuitry. In response to the fast selection signal, the control logic circuitry performs data access commands at a fast rate, while in response to the slow selection signal, the control logic circuitry executes such commands at a slower, more conservative rate.

Abstract: During compression mode testing of a semiconductor memory device, a memory address is compressed to free up 2 or more bits in the address (e.g., an 11-bit address is compressed to 9-bits, freeing up 2 bits). Redundant element enable circuitry is coupled to one or more pins on a packaged chip that are unused during the compression mode testing. The circuitry receives control signals from external testing circuitry to select between the primary memory array in the chip, and redundant rows and columns of memory in the chip. As a result, during compressed address mode testing of the chip, a full 11-bit word is input to test the circuitry, but where 2 of the 11 bits allow the external circuitry to toggle between, and thereby selectively access, the rows and columns of primary and redundant memory in the chip. Alternatively, the circuitry can also be coupled to a non-connected pin on the packaged chip so as to operate during a non-compression mode testing.

Abstract: A single pull-up circuit is shared between a redundant row antifuse cell, and a redundant column antifuse cell. Additionally, a single selection circuit is shared between the two antifuse cells. A row selection signal supplied thereto selects the antifuse cell for the redundant row, while a column selection signal selects the antifuse cell for the redundant column. A small channel length transistor is employed within the latch circuit. As a result, the latch can quickly pull up a value when the antifuse cell is not blown, and quickly latch that value within the latch since an RC time constant of the latch is decreased. A pulsed pull-up signal having a very short duration is employed to enable the latch. Since the pulsed pull-up signal has a short duration, a high voltage supply V.sub.CC is provided through the latch and a blown antifuse cell to ground for only a short duration, thereby minimizing the possibility of such a low resistance current path from damaging the circuitry.