Patents Assigned to Micron Technology, In.
  • Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
    Patent number: 9165888
    Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Warren M. Farnworth, David R. Hembree
  • Sensing operations in a memory device
    Patent number: 9165664
    Abstract: Methods and apparatus for sensing operations in memory devices are disclosed. In at least one embodiment, a sensing operation to determine negative threshold voltages in memory cells by an elevated source potential applied to a string of memory cells and an elevated data line potential applied to the string of memory cells is disclosed. A ramped sense potential is incorporated into the sense operation according to at least one embodiment. A sense circuit diode allows a sense potential to fall below a data line potential during a sensing operation according to another embodiment.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Andrea D'Alessandro, Violante Moschiano
  • Determining sector status in a memory device
    Patent number: 9165653
    Abstract: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Siamack Nemazie
  • Read bias management to reduce read errors for phase change memory
    Patent number: 9164829
    Abstract: During a read process for a memory device, such as a phase change memory device, a bias condition can be applied to a memory cell to determine the memory cell's state. The determined state of the memory cell can depend on a threshold voltage of the memory cell. The threshold voltage of the memory cell may shift over time. The shift in threshold voltage may result in read errors. The applied bias condition may be modified based on the resulting read errors.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Apparatuses including electrodes having a conductive barrier material and methods of forming same
    Patent number: 9166158
    Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Swapnil A. Lengade, John M. Meldrim, Andrea Gotti
  • Memory cells, methods of forming memory cells and methods of forming memory arrays
    Patent number: 9166156
    Abstract: Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, John K. Zahurak
  • Method and apparatus providing analytical device and operating method based on solid state image sensor
    Patent number: 9164040
    Abstract: An analytical system-on-a-chip can be used as an analytical imaging device, for example, for detecting the presence of a chemical compound. A layer of analytical material is formed on a transparent layer overlying a solid state image sensor. The analytical material can react in known ways with at least one reactant to block light or to allow light to pass through to the array. The underlying sensor array, in turn, can process the presence, absence or amount of light into a digitized signal output. The system-on-a-chip may also include software that can detect and analyze the output signals of the device.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Terry L. Gilton
  • Charge pump apparatus, a memory integrated circuit and methods of power supply
    Patent number: 9165666
    Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit. A charge pump apparatus and a memory integrated circuit are also described.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: October 20, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Dumitru Cioaca
  • Applying a voltage-delay correction to a non-defective memory block that replaces a defective memory block based on the actual location of the non-defective memory block
    Patent number: 9165681
    Abstract: In an embodiment, a defective memory block is replaced with a non-defective memory block, and a voltage-delay correction is applied to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Dzung H. Nguyen, William H. Radke
  • Devices, systems, and methods to synchronize parallel processing of a single data stream
    Patent number: 9164945
    Abstract: Disclosed are methods and devices, among which is a system that includes one or more pattern-recognition processors, such as in a pattern-recognition cluster. The pattern-recognition processors may be activated to perform a search of a data stream individually using a chip select or in parallel using a universal select signal. In this manner, the plurality of pattern-recognition processors may be enabled concurrently for synchronized processing of the data stream.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Semiconductor constructions and methods of forming memory cells
    Patent number: 9166159
    Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Carmela Cupeta, Andrea Redaelli, Paolo Giuseppe Cappelletti
  • Logical address translation
    Patent number: 9164701
    Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Martin L. Culley, Troy A. Manning, Troy D. Larsen
  • Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
    Patent number: 9164937
    Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Douglas A. Larson, Jeffrey J Cronin
  • Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
    Patent number: 9165688
    Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Chris Bueb, Sean Eilert
  • Methods and apparatuses for shifting data signals to match command signal delay
    Patent number: 9166579
    Abstract: Methods and apparatuses for shifting data signals are disclosed herein. An apparatus may comprise a clock generation circuit, a delay path, and a driver. The clock generation circuit may be configured to receive an input clock signal and generate a plurality of clock signals based, at least in part, on the clock signal. A delay path may be coupled to the clock generation circuit and configured to receive the input clock signal and the plurality of clock signals. The delay path may be further configured to receive a data signal and delay the data signal based, at least in part, on the input clock signal and each of the plurality of clock signals. A driver may be coupled to the delay path and configured to receive the delayed data signal, and may further be configured to provide the delayed data signal to a bus.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Brian Huber, Parthasarathy Gajapathy
  • Memory having internal processors and methods of controlling memory access
    Patent number: 9164698
    Abstract: Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, Dan Skinner, J. Thomas Pawlowski
  • Staggered programming for resistive memories
    Patent number: 9164894
    Abstract: Subject matter disclosed herein relates to a memory device and method of programming same. In some embodiments, a memory device can be programmed by partitioning information into a plurality of chunks. Partitioning can be performed by determining a pattern of logic ones and zeroes, and setting a size of an information chunk based on the pattern of logic ones and zeroes.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gerald Barkley, Sunil Shetty, Andrea Martinelli
  • Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods
    Patent number: 9166107
    Abstract: Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Ji-Soo Park
  • Disturb verify for programming memory cells
    Patent number: 9165658
    Abstract: Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing a disturb verify operation on a second memory cell adjacent to the first memory cell, and inhibiting the first memory cell from further programming in response to the second memory cell failing the disturb verify operation. Other apparatuses and methods are also disclosed.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Akira Goda
  • Methods and systems to accomplish variable width data input
    Patent number: 9164940
    Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes