Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalk of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.

Abstract: Apparatuses and methods for providing and interpreting command packets for direct control of memory channels are disclosed herein. An example apparatus includes flash memories configured into channels and a controller coupled to the flash memories. The controller receives packets and interpret the packets based at least on a first protocol, and determines whether any packets are linked based on a link identifier included in a block of each packet. The controller arranges the subset of packets based on an index included in the block of each packet of the subset of packets, and the subset of packets are arranged in order based on the respective indexes. A target flash memory and a target channel are determined by the controller based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets.

Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed.

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

Abstract: Integrated circuit structures, as well as methods for their formation, might include a semiconductor material, a first active area in the semiconductor material, a second active area in the semiconductor material, and an isolation structure comprising a dielectric material deposited in a trench formed in the semiconductor material between the first active area and the second active area. The isolation structure might further include a first edge portion extending below a surface of the semiconductor material to a first depth, a second edge portion extending below the surface of the semiconductor material to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor material to a second depth, less than the first depth.

Abstract: A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

Abstract: An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

Abstract: A memory device to search for a voltage optimized to read a group of memory cells. In response to a read command, the memory device measures first signal and noise characteristics of the memory cells by reading the memory cells at first test voltages. Based on the first signal and noise characteristics, the memory device may determine that the optimized read voltage is outside of a range of the first test voltages. In response, the memory device determines, based on the first signal and noise characteristics, an estimate of the optimized read voltage, and measures second signal and noise characteristics by reading at second test voltages configured around the estimate. The optimized read voltage can be computed based at least in part on the second signal and noise characteristics. The memory device retrieves data from the memory cells using the optimized read voltage.

Abstract: Systems, apparatuses, and methods to implement time to live for memory access by processors. For example, a processor has a register configured to store a parameter specifying a time duration indicative of the desired time to live. A memory system has multiple components with different latencies for memory access. When the memory controller of the processor sends a command to the memory system to load an item from a memory address, the memory system can fail to provide, to the processor within the time duration, the item from the memory address currently being hosted in a first component. In response, the memory controller can send a signal to abort the command; and the memory system can select a second component having a memory access latency shorter than the first component, and change the hosting of the memory address from in the first component to in the second component.

Abstract: Memory cells are described that include two reference voltages that may store and sense three distinct memory states by compensating for undesired intrinsic charges affecting a memory cell. Although embodiments described herein refer to three memory states, it should be appreciated that in other embodiments, the memory cell may store or sense more than three charge distributions using the described methods and techniques. In a first memory state, a programming voltage or a sensed voltage may be higher than a first reference voltage and a second reference voltage. In a second memory state, the applied voltage or the sensed voltage may be between the first and the second reference voltages. In a third memory state, the applied voltage or the sensed voltage may be lower than the first and the second reference voltages. As such, the memory cell may store and retrieve three memory states.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.

Abstract: A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another.

Abstract: An apparatus can have a processor configured to determine a length of time that a vehicle is in a region and to determine whether the vehicle needs to be configured for the region based on the determined length of time. Configuring a vehicle can include configuring updating the software/firmware of the vehicle.

Abstract: A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of the memory sub-system is determined. The value is compared to a threshold level corresponding to the first sequence of operations to determine whether a condition is satisfied. In response to satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.

Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.

Abstract: Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.