Abstract: The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a phase change material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values.

Abstract: A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic layers are formed having widened regions at the ends of the layers. As such, the shape made out by the magneto-resistive memory, from a top-view perspective, is wide at the ends and narrower at the mid-, forming an I shape in one preferred embodiment. The end portions of the free magnetic layer are allowed to magnetically couple to the end portions of the pinned magnetic layer such that magnetic coupling is shifted to these widened regions and coupling in the mid-portion between the widened regions is minimized. Thus, the influence of the pinned magnetic layer on the magnetization orientation of the mid-portion of the free magnetic layer is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.

Abstract: Self refresh timing in a low-power dynamic memory system is governed by an oscillator having a voltage dependent resistor and a process dependent capacitor. The resistor increases in resistance to compensate for increased applied power supply voltage and variation in substrate bias voltage. The total capacitance needed for a given oscillator center frequency is made up of a plurality of capacitors having the same physical characteristics as the capacitor used in the dynamic memory cell. Power supply voltage, substrate bias voltage, and the physical characteristics of the cell capacitor affect the cell's data retention time. By compensating the oscillator for these effects, refreshing is optimally accomplished within the data retention time. A system having compensated refresh timing according to the invention is more appropriate for low power applications due to the resulting decreased power consumption.