Patents Assigned to Micron Technology
  • Auto-power on mode for biased testing of a power management integrated circuit (PMIC)
    Patent number: 11538545
    Abstract: Methods, systems, and devices supporting an auto-power on mode for biased testing of a power management integrated circuit (PMIC) are described. A system may program a PMIC of a memory system to a specific mode. The mode may cause the PMIC to apply a bias to a memory device of the memory system upon receiving power and independent of a command to apply the bias to the memory device. The system may transmit power to the memory system while controlling one or more operating conditions (e.g., temperature, humidity) for a threshold time. The PMIC may apply a bias to the memory device during the threshold time based on the PMIC being programmed to the mode and the transmitted power. The system may identify a capability or defect of the memory device resulting from transmitting the power to the memory system while controlling the operating conditions for the threshold time.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: William Anthony Lendvay
  • Column selector architecture with edge mat optimization
    Patent number: 11538516
    Abstract: A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Hiroshi Akamatsu
  • Memory element for weight update in a neural network
    Patent number: 11538513
    Abstract: An output, representing synaptic weights of a neural network can be received from first memory elements. The output can be compared to a known correct output. A random number can be generated with a tuned bias via second memory elements. The weights can be updated based on the random number and a difference between the output and the known correct output.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Fabio Pellizzer
  • Methods of forming a memory cell comprising a metal chalcogenide material
    Patent number: 11538991
    Abstract: A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting the metal precursor and the chalcogenide precursor to form a metal chalcogenide material on a substrate. The metal precursor is a carboxylate of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid. The chalcogenide precursor is a hydride, alkyl, or aryl precursor of sulfur, selenium, or tellurium or a silylhydride, silylalkyl, or silylaryl precursor of sulfur, selenium, or tellurium. Methods of forming a memory cell including the metal chalcogenide material are also disclosed, as are memory cells including the metal chalcogenide material.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Eugene P. Marsh, Stefan Uhlenbrock
  • Cold data detector in memory system
    Patent number: 11537306
    Abstract: A cold data detector circuit includes a bubble break register that is configured to detect cold data in a memory system including main memory and secondary memory. The bubble break register selectively shifts received segment addresses to fill empty slots without having to wait until the empty slots are shifted out an end slot, and may provide an indication of cold data in response to every slot of the register being filled with a different respective segment address.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Daigo Toyama
  • Transistors and arrays of elevationally-extending strings of memory cells
    Patent number: 11538919
    Abstract: A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ramanathan Gandhi, Augusto Benvenuti, Giovanni Maria Paolucci
  • Single field for encoding multiple elements
    Patent number: 11539623
    Abstract: Implementations of the present disclosure are directed to systems and methods for reducing the size of packet headers by using a single field to encode multiple elements. Instead of including separate fields for each element, one or more encoded fields may be used, each of which is decoded to determine two or more values for the data packet. A receiving device decodes the encoded data field to retrieve the two or more values.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Tony Brewer
  • Methods and systems for hermetically sealed fiber to chip connections
    Patent number: 11536915
    Abstract: Disclosed are methods of providing a hermetically sealed optical connection between an optical fiber and an optical element of a chip and a photonic-integrated chip manufactured using such methods.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Gurtej Sandhu
  • Methods for edge trimming of semiconductor wafers and related apparatus
    Patent number: 11538711
    Abstract: Methods and apparatus for pre-treating semiconductor wafers before edge trimming to enhance wafer edge quality prior to thinning the semiconductor wafers from an initial thickness, and increasing yield post-thinning of the pre-treated, edge trimmed semiconductor wafers.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Jing-Cheng Lin
  • Metal insulator semiconductor (MIS) contact in three dimensional (3D) vertical memory
    Patent number: 11538809
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Deepak Chandra Pandey, Litao Yang, Srinivas Pulugurtha, Yunfei Gao, Haitao Liu
  • Translating of logical address to determine first and second portions of physical address
    Patent number: 11537526
    Abstract: Methods, systems, and devices for data alignment for logical to physical table compression are described. A controller coupled with the memory array may receive a command to access a logical block address associated with a memory device. In some cases, a first portion of a physical address of the memory device associated with the logical block address may be identified. The controller may perform an operation on the logical block address included in the command and identify a second portion of the physical address based on performing the operation. The physical address of the memory device may be accessed based on identifying the first portion and the second portion.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David A. Palmer
  • Integrated Assemblies Having Voids Along Regions of Gates, and Methods of Forming Conductive Structures
    Publication number: 20220406785
    Abstract: Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 22, 2022
    Applicant: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Integrated Assemblies and Methods of Forming Integrated Assemblies
    Publication number: 20220406899
    Abstract: Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Yoshitaka Nakamura, Devesh Dadhich Shreeram, Yi Fang Lee, Scott E. Sills, Jerome A. Imonigie, Kaustubh Shrimali
  • Multi-Rail Power Transition
    Publication number: 20220406357
    Abstract: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 22, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Hyun Yoo Lee, Keun Soo Song
  • Write Timing Compensation
    Publication number: 20220406365
    Abstract: This document describes apparatuses and techniques for write timing compensation. In various aspects, a write timing compensator of a memory controller can apply a delay to data signals transmitted to a memory circuit based on various operating parameters, which may include voltage or latency information. In some cases, the memory controller or memory circuit powers components of write timing compensation circuitry using a dynamic power rail that scales with an operating voltage of the memory circuit. By so doing, the write timing compensator or compensation circuits may improve signal integrity of data signals communicated between the memory controller and the memory circuit at different frequencies and voltages.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 22, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Keun Soo Song, Hyun Yoo Lee
  • Scalable memory system protocol supporting programmable number of levels of indirection
    Patent number: 11531472
    Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventor: J. Thomas Pawlowski
  • Self-assembled nanostructures including metal oxides and semiconductor structures comprised thereof
    Patent number: 11532477
    Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nicholas Hendricks, Adam L. Olson, William R. Brown, Ho Seop Eom, Xue Chen, Kaveri Jain, Scott Schuldenfrei
  • Multi-level receiver with termination-off mode
    Patent number: 11531632
    Abstract: Methods, systems, and devices for multi-level receivers with various operating modes (e.g., on-die termination mode, termination-off mode, etc.) are described. Different modes may be utilized for receiving different types of signaling over a channel. Each mode may correspond to the use of a respective set of receivers configured for the different types of signaling. For example, a device may include a first set of receivers used to receive a first type of signal (e.g., with the channel being actively terminated) and a second set of receivers used to receive a second type of signal (e.g., with the channel being non-terminated). When communicating with another device, based on the type of signaling used for communications, either the first set of receivers or the second set of receivers may be enabled (e.g., through selecting a receiver path for the corresponding mode).
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Martin Brox, Wolfgang Anton Spirkl, Thomas Hein, Michael Dieter Richter, Peter Mayer
  • Error correcting code poisoning for memory devices and associated methods and systems
    Patent number: 11533064
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to poison data based on an indication provided by a host device coupled with the memory devices. The indication may include which one or more bits to poison (invert) at which stages of performing write or read operations. In some embodiments, the memory device may invert one or more bits according to the indication and then correct one or more errors associated with inverting the one or more bit to verify its on-die ECC functionality. In some embodiments, the memory device may provide the host device with poisoned data including one or more bits inverted according to the indication such that the host device may test system-level ECC functionality using the poisoned data.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Joshua E. Alzheimer, Randall J. Rooney
  • Data transfer in port switch memory
    Patent number: 11531490
    Abstract: The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Frank F. Ross