Abstract: A computer program generates a wire routing pattern that connects one driver with a plurality of receivers. The overlapping length of each vector pair, which consists of any two vectors headed from the driver to the receivers, is calculated. One vector pair that has the greatest overlapping length is selected. For the selected vector pair, three kinds of common nodes are created, each of which is used to make a common path part of the way to the receivers, to generate three kinds of renewed vector patterns. The operations are repeated and plural candidate routing patters are acquired. One candidate routing pattern having the smallest total wiring length is selected as the optimum routing pattern. If there exist plural patterns that have the same smallest total wiring length, one pattern can be selected that has the smallest one of the greatest. D-R path lengths.

Abstract: A computer program generates a wire routing pattern that connects one driver with a plurality of receivers. The overlapping length of each vector pair, which consists of any two vectors headed from the driver to the receivers, is calculated. One vector pair that has the greatest overlapping length is selected. For the selected vector pair, three kinds of common nodes are created, each of which is used to make a common path part of the way to the receivers, to generate three kinds of renewed vector patterns. The operations are repeated and plural candidate routing patters are acquired. One candidate routing pattern having the smallest total wiring length is selected as the optimum routing pattern. If there exist plural patterns that have the same smallest total wiring length, one pattern can be selected that has the smallest one of the greatest D-R path lengths.

Abstract: An IC device (10) held on an IC carrier (24) is a double-sided electrode type BGA IC device (10) provided with bump electrodes (14) on a first surface of a package. The IC device has, on a second surface opposite the first surface, (a) a central protrusion (30), (b) a peripheral portion (32) lower than the protrusion by one step, and (c) upper electrodes (18) formed on the peripheral portion of the IC device. The IC carrier is provided with a frame (36), a cover (40), and a holding means (42). The frame forms a device reception space (38) for receiving the IC device. The cover can cover the upper electrodes while in contact with the periphery of the IC device held on the IC carrier. The holding means can hold the IC device on the IC carrier with the cover covering the upper electrodes of the IC device. The IC device can be set in an IC socket while being mounted on the IC carrier.

Abstract: A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the first conductor layer, which includes through-hole junction pads, flatness improvement rings surrounding the through-hole junction pads and a grounding region further surrounding the flatness improvement rings. Since the flatness improvement rings are located around the through-hole junction pads, the surface of the first insulating layer, which is located above the first conductor layer, is free from severe undulation even near the through-hole junction pads. Accordingly, the multilayer wiring division has less irregularity in shape as a whole, and thus the probe mounting pads on the surface of the second insulating layer do not slope but keep almost horizontal. The probe unit substrate according to the invention has an advantage of less surface undulation and having non-sloping probe mounting pads without using a complicated manufacturing process.

Abstract: A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. One of the conductor layers has a grounded pattern. Each of the conductor layers has a reference pattern, which is usable as a standard in calculation of an electric capacitance. An electric capacitance is measured between the grounded pattern and the three-dimensional wiring path. On the other hand, a theoretical electrical capacitance is calculated on the basis of a reference value of electric capacitance which has been measured between the reference pattern and the grounded pattern. The measured value for the wiring path is compared to the calculated value to determine whether the three-dimensional wiring path is good or bad. As the multilayer wiring section has the reference patterns, the electric capacitance for the normal wiring path can be obtained by calculation without preparing the normal acceptable product.

Abstract: A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. The ceramic substrate has an internal conductor layer, which is connected to a test pad. The first conductor layer is formed, and then an electric capacitance is measured between the test pad and a wiring pattern of the first conductor layer. On the other hand, an electrical capacitance is calculated under the normal wiring pattern condition. The measured value is compared to the calculated value to determine whether the wiring pattern is good or bad. Similar measurements and comparisons are carried out for each of the second through fifth conductor layers to determine whether a three-dimensional wiring path is good or bad. As the ceramic substrate has an internal conductor layer, the electric capacitance of the wiring can be measured without an overall grounded layer in the multilayer wiring section, which is a characteristic part different from others among a variety of the multilayer wiring boards.

Abstract: A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the first conductor layer, which includes through-hole junction pads, flatness improvement rings surrounding the through-hole junction pads and a grounding region further surrounding the flatness improvement rings. Since the flatness improvement rings are located around the through-hole junction pads, the surface of the first insulating layer, which is located above the first conductor layer, is free from severe undulation even near the through-hole junction pads. Accordingly, the multilayer wiring division has less irregularity in shape as a whole, and thus the probe mounting pads on the surface of the second insulating layer do not slope but keep almost horizontal. The probe unit substrate according to the invention has an advantage of less surface undulation and having non-sloping probe mounting pads without using a complicated manufacturing process.

Abstract: A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the first conductor layer, which includes through-hole junction pads, flatness improvement rings surrounding the through-hole junction pads and a grounding region further surrounding the flatness improvement rings. Since the flatness improvement rings are located around the through-hole junction pads, the surface of the first insulating layer, which is located above the first conductor layer, is free from severe undulation even near the through-hole junction pads. Accordingly, the multilayer wiring division has less irregularity in shape as a whole, and thus the probe mounting pads on the surface of the second insulating layer do not slope but keep almost horizontal. The probe unit substrate according to the invention has an advantage of less surface undulation and having non-sloping probe mounting pads without using a complicated manufacturing process.

Abstract: A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. The ceramic substrate has an internal conductor layer, which is connected to a test pad. The first conductor layer is formed, and then an electric capacitance is measured between the test pad and a wiring pattern of the first conductor layer. On the other hand, an electrical capacitance is calculated under the normal wiring pattern condition. The measured value is compared to the calculated value to determine whether the wiring pattern is good or bad. Similar measurements and comparisons are carried out for each of the second through fifth conductor layers to determine whether a three-dimensional wiring path is good or bad. As the ceramic substrate has an internal conductor layer, the electric capacitance of the wiring can be measured without an overall grounded layer in the multilayer wiring section, which is a characteristic part different from others among a variety of the multilayer wiring boards.

Abstract: A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. One of the conductor layers has a grounded pattern. Each of the conductor layers has a reference pattern, which is usable as a standard in calculation of an electric capacitance. An electric capacitance is measured between the grounded pattern and the three-dimensional wiring path. On the other hand, a theoretical electrical capacitance is calculated on the basis of a reference value of electric capacitance which has been measured between the reference pattern and the grounded pattern. The measured value for the wiring path is compared to the calculated value to determine whether the three-dimensional wiring path is good or bad. As the multilayer wiring section has the reference patterns, the electric capacitance for the normal wiring path can be obtained by calculation without preparing the normal acceptable product.

Abstract: An IC device (10) held on an IC carrier (24) is a double-sided electrode type BGA IC device (10) provided with bump electrodes (14) on a first surface of a package. The IC device has, on a second surface opposite the first surface, (a) a central protrusion (30), (b) a peripheral portion (32) lower than the protrusion by one step, and (c) upper electrodes (18) formed on the peripheral portion of the IC device. The IC carrier is provided with a frame (36), a cover (40), and a holding means (42). The frame forms a device reception space (38) for receiving the IC device. The cover can cover the upper electrodes while in contact with the periphery of the IC device held on the IC carrier. The holding means can hold the IC device on the IC carrier with the cover covering the upper electrodes of the IC device. The IC device can be set in an IC socket while being mounted on the IC carrier.

Abstract: A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the first conductor layer, which includes through-hole junction pads, flatness improvement rings surrounding the through-hole junction pads and a grounding region further surrounding the flatness improvement rings. Since the flatness improvement rings are located around the through-hole junction pads, the surface of the first insulating layer, which is located above the first conductor layer, is free from severe undulation even near the through-hole junction pads. Accordingly, the multilayer wiring division has less irregularity in shape as a whole, and thus the probe mounting pads on the surface of the second insulating layer do not slope but keep almost horizontal. The probe unit substrate according to the invention has an advantage of less surface undulation and having non-sloping probe mounting pads without using a complicated manufacturing process.