Abstract: The Advanced Encryption Standard (AES) cipher can be performed in a manner that preserves the secrecy of cryptographic keys, even under the intense scrutiny of a reverse-engineer observing every aspect of the computation. A method can include loading a key in a non-standard representation. The method can also include processing the key with respect to data in at least three first type rounds and a plurality of second type rounds. The processing the key with respect to data can include either encrypting the data using the key or decrypting the data using the key. The first type rounds can be configured to maintain an order of channels of bits at an output from the order of corresponding channels of bits at an input. The second type rounds can be configured to vary the order of channels of bits at an output from the order of corresponding channels of bits at an input.

Abstract: A Planar Inverted-F Wing Antenna (PIFWA) device, system, and method used for commercial and residential induction cooking tops, ovens, combo-steamers, and pressure cookers. The outline of the PIFWA is an isosceles triangle with a truncated vertex end opposite the base side. The PIFWA transmits and receives (TX/RX) signals with wireless sensors including Surface Acoustic Wave (SAW) devices. The antenna comprises a device, system, and method to monitor the cooking process and temperature of food. Embodiments of the PIFWA antenna operate at about 433 MHz, have a feed between two slots, and a shorting plate at the opposing end. Antenna location and alignment within the culinary appliance provides uniform signal strength and gain performance in the regions occupied by one or more sensors.

Abstract: A dual port pass through midspan constituted of: a first port arranged for connection to a first data terminal equipment over a first data communication cabling; a second port arranged for connection to a second data terminal equipment over a second data communication cabling; a first power sourcing equipment arranged to inject power on two of the 4 wire pairs of the first data communication cabling; a second power sourcing equipment arranged to inject power on two of the 4 wire pairs of the second data communication cabling; and a data pass through connection arranged to pass high speed data signals between the first port to the second port, the data pass through connection comprising a direct current blocking circuit arranged to: prevent power from the first power sourcing equipment from appearing at the second port; and prevent power from the second power sourcing equipment from appearing at the first port.

Abstract: A sense current generation apparatus constituted of: a main electronically controlled switch arranged to provide a current path for an input current; a sense electronically controlled switch arranged to generate a sense current; a voltage matching circuit arranged to adjust the voltage across the first and second terminals of the sense switch to equal the voltage across the first and second terminals of the main switch, within a predetermined maximum error voltage, such that the sense current is representative of the input current; and a voltage governor arranged to: receive an indication of the voltage across the first and second terminals of the main switch; and responsive to the received voltage indication, adjust the control voltage of the main switch such that the absolute value of the voltage across the terminals thereof is maintained above a predetermined voltage threshold greater than a boundary of the error range.

Abstract: A twin power sourcing equipment constituted of: a first power sourcing equipment; and a second power sourcing equipment arranged for connection to a powered device over respective power paths; the first and second power sourcing equipments arranged to: simultaneously perform detection of the powered device; and in the event that at least one of the first and second power sourcing equipments detects the presence of the powered device, alternately perform detection of the powered device to detect a signature impedance; and in the event that each of the alternate detection is indicative of the presence of the signature impedance, provide power to the powered device simultaneously by the first and second power sourcing equipment. Power is not provided to the powered device in the event that the simultaneous detection is indicative of the absence of the powered device on each of the first path and the second path.

Abstract: A method of providing a wide range of input currents for an analog to digital converter (ADC), the method constituted of: receiving an input current; selecting one of a plurality of selectable ratios; and generating at least one sense current, the magnitudes of the at least one generated sense current and the received input current exhibiting the selected ratio, wherein the ADC is arranged to receive a voltage representation of the at least one generated sense current.

Abstract: A powered device interface arranged as an interface between power received over a structured communication cabling and a powered device, the powered device interface constituted of: a class event counter; a logic circuit in communication with the class event counter; and a plurality of flag outputs each responsive to the logic circuit, each of the flag outputs associated with a predetermined powering level of a power sourcing equipment connected over the structured communication cabling, the logic circuit arranged to: output an active signal at the flag output associated with a detected powering level of the connected power sourcing equipment; and output an active signal at all other flag outputs associated with powering levels less than the detected powering level of the connected power sourcing equipment.

Abstract: A power saving arrangement for use with a phase cut dimmer, the power saving arrangement constituted of: a power converter arranged to convert a received alternating current power signal to a direct current signal; a detector arranged to detect the presence, or absence, of the phase cut dimmer blocking a portion of an alternating current mains power sine wave from reaching the power converter; and a controllable minimum holding current circuit in communication with the received alternating current power signal, the controllable minimum holding current circuit responsive to an output of the detector, wherein in the event that the detector detects the absence of the phase cut dimmer, the controllable minimum holding current circuit is disabled such that a minimum holding current is not provided.

Abstract: A port current control arrangement, constituted of: a current source arranged to generate a reference current or a predetermined value; an on-chip reference resistor, the generated reference current arranged to produce a reference voltage across the on-chip reference resistor; an on-chip sense resistor, a port current arranged to flow through the on-chip sense resistor and produce a sense voltage across the on-chip sense resistor, wherein the resistance of the on-chip sense resistor exhibits a predetermined relationship with the resistance of the first on-chip reference resistor; and a current control circuit, a first input of the current control circuit arranged to receive the produced reference voltage and a second input of the current control circuit arranged to receive the sense voltage, wherein the current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage.

Abstract: A power sourcing equipment (PSE) exhibiting a low power sleep mode, the PSE constituted of: a sleep control circuitry comprising a first timer; an effective resistance threshold detector responsive to the sleep control circuitry and arranged to detect whether the effective resistance across the output port of the PSE is less than a predetermined threshold; and a detection and powering circuitry responsive to the sleep control circuitry, wherein the sleep control circuitry is arranged to load the first timer with a first predetermined time period, and at the expiration of the first predetermined time period: activate the effective resistance threshold detector for a second predetermined time period; and in the event the effective resistance threshold detector detects that the effective resistance across the output port of the PSE is less than the predetermined threshold, enable the detection and powering circuitry.

Abstract: A power over Ethernet extender arranged to detect if power is received over 2 pairs of wires or over 4 pairs of wires. If power is received over 4 pairs of wires, power is output over only 2 pairs of wires. Preferably, the power signature of the received power is further detected. If the incoming power over a first 2 pairs of wires supports in excess of 13 watts of power consumption, and power is received over 4 pairs, then the output power supports in excess of 13 watts of power consumption; and if the incoming power over a first 2 pairs of wires supports in excess of 13 watts of power consumption, and power is not received over 4 pairs, then the output power does not support in excess of 13 watts of power consumption.

Abstract: An input circuitry for an ADC constituted of: a first resistor coupled to an input of the ADC; a second resistor coupled to the input of the ADC and arranged to provide a current path; an electronically controlled switch coupled to the first resistor and arranged to provide a parallel current path through the first resistor; and a control circuitry; wherein the control circuitry is arranged to operate in a high current mode in the event that the input current exhibits an intensity within a first predetermined range and is arranged to operate in a low current mode in the event that the input current exhibits an intensity within a second predetermined range, different than the first predetermined range, wherein, in the high current mode the control circuitry is arranged to close the electronically controlled switch and in the low current mode is arranged to open the electronically controlled switch.

Abstract: A multiplexed sigma delta modulator constituted of: a control circuitry; a multiplexer responsive to the control circuitry and arranged to receive a plurality of input signals; a comparing circuit, a first input of the comparing circuit coupled to the output of the multiplexer; an integrator, the input of the integrator coupled to the output of the comparing circuit; a latched comparing circuit, one input of the latched comparing circuit coupled to the output of the integrator; a plurality of storage elements, each associated with one of the plurality of inputs; and a feedback circuit arranged to feedback the output of the latched comparing circuit to the second input of the comparing circuit, wherein the control circuitry is further arranged to store the charge of an element of the integrator on the associated storage element when the associated signal is not passed by the multiplexer to the output of the multiplexer.

Abstract: A port current control arrangement, constituted of: a current source arranged to generate a reference current or a predetermined value; an on-chip reference resistor, the generated reference current arranged to produce a reference voltage across the on-chip reference resistor; an on-chip sense resistor, a port current arranged to flow through the on-chip sense resistor and produce a sense voltage across the on-chip sense resistor, wherein the resistance of the on-chip sense resistor exhibits a predetermined relationship with the resistance of the first on-chip reference resistor; and a current control circuit, a first input of the current control circuit arranged to receive the produced reference voltage and a second input of the current control circuit arranged to receive the sense voltage, wherein the current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage.

Abstract: An input circuitry for an ADC constituted of: a first resistor coupled to an input of the ADC; a second resistor coupled to the input of the ADC and arranged to provide a current path; an electronically controlled switch coupled to the first resistor and arranged to provide a parallel current path through the first resistor; and a control circuitry; wherein the control circuitry is arranged to operate in a high current mode in the event that the input current exhibits an intensity within a first predetermined range and is arranged to operate in a low current mode in the event that the input current exhibits an intensity within a second predetermined range, different than the first predetermined range, wherein, in the high current mode the control circuitry is arranged to close the electronically controlled switch and in the low current mode is arranged to open the electronically controlled switch.

Abstract: A dual port pass through midspan constituted of: a first port arranged for connection to a first data terminal equipment over a first data communication cabling; a second port arranged for connection to a second data terminal equipment over a second data communication cabling; a first power sourcing equipment arranged to inject power on two of the 4 wire pairs of the first data communication cabling; a second power sourcing equipment arranged to inject power on two of the 4 wire pairs of the second data communication cabling; and a data pass through connection arranged to pass high speed data signals between the first port to the second port, the data pass through connection comprising a direct current blocking circuit arranged to: prevent power from the first power sourcing equipment from appearing at the second port; and prevent power from the second power sourcing equipment from appearing at the first port.

Abstract: A twin power sourcing equipment constituted of: a first power sourcing equipment; and a second power sourcing equipment arranged for connection to a powered device over respective power paths; the first and second power sourcing equipments arranged to: simultaneously perform detection of the powered device; and in the event that at least one of the first and second power sourcing equipments detects the presence of the powered device, alternately perform detection of the powered device to detect a signature impedance; and in the event that each of the alternate detection is indicative of the presence of the signature impedance, provide power to the powered device simultaneously by the first and second power sourcing equipment. Power is not provided to the powered device in the event that the simultaneous detection is indicative of the absence of the powered device on each of the first path and the second path.

Abstract: A solid state lighting controller arranged for use with a single stage power factor correction switched mode power supply, a light emitting diode (LED) string and a current sense element arranged to sense current through the LED string, the solid state lighting controller constituted of: a current governor in series with the LED string exhibiting a governor differential amplifier and a governor electronically controlled switch responsive to the output of the governor differential amplifier, the current governor arranged to limit current flow through the LED string responsive to a current limit reference; and a feedback circuit exhibiting an error amplifier, the feedback circuit arranged to feedback a signal to the power factor correction switched mode power supply controller whose value is a function of the difference between the current through the LED string sensed by the current sense element and a target current signal.

Abstract: A phase cut angle converter with range detection for a phase cut dimmer constituted of: a phase cut angle detector arranged to detect the phase cut angle presented by the phase cut dimmer blocking a portion of an alternating current mains power sine wave from reaching a power converter, and output a signal whose value is responsive to the detected phase cut angle; a storage functionality constituted of a memory in communication with the phase cut angle detector, the storage functionality arranged to detect each of a minimum value and a maximum value for the detected phase cut angle of the phase cut angle detector and store the minimum value and the maximum value on the memory; and a signal adjustment functionality arranged to convert the detected phase cut angle to a dimming signal responsive to the stored minimum value and the maximum value for the detected phase cut angle.

Abstract: A powered device interface arranged as an interface between power received over a structured communication cabling and a powered device, the powered device interface constituted of: a class event counter; a logic circuit in communication with the class event counter; and a plurality of flag outputs each responsive to the logic circuit, each of the flag outputs associated with a predetermined powering level of a power sourcing equipment connected over the structured communication cabling, the logic circuit arranged to: output an active signal at the flag output associated with a detected powering level of the connected power sourcing equipment; and output an active signal at all other flag outputs associated with powering levels less than the detected powering level of the connected power sourcing equipment.