Abstract: In a network including a controllable device, a method for sending a network management method to the controllable device including asserting a network management command directed to the controllable device and in response to the network management command generating and sending over the network a first number of WOL packets having a predetermined relationship to one another, followed by generating and sending over the network a second number of WOL packets, a predetermined relationship between the second number of WOL packets defining the network management command.

Abstract: A mark and hold system comprising a main power supply, a mark voltage power supply and a detection current source. After detection, and optionally classification, the main power supply is disconnected from the PD and instead the PD is connected to the mark voltage power supply. The detection current source draws current through a port resistance of the PSE and the PD. The voltage across the port resistance is monitored to determine whether the PD is still connected to the port.

Abstract: A stacked RJ45 modular jack assembly includes a lower RJ45 jack portion having a bottom surface adapted to be mounted on a printed circuit board, the lower RJ45 jack having a plurality of lower connection fingers 1 through 8, an upper RJ45 jack portion disposed above the lower RJ45 jack portion the upper RJ45 jack having a plurality of upper connection fingers 1 through 8, and a data/RF components block including RF components, the data/RF components block mounted directly behind a rear surface of the stacked RJ45 modular jack assembly.

Abstract: An inrush current limiting method not requiring the use of a sense resistor, the method constituted of: generating a ramped voltage; comparing a first function of a voltage across a port capacitor with the generated ramp voltage; responsive to the outcome of the comparison of the voltage first function with the ramp voltage, controlling an electronically controlled switch coupled to the port capacitor such that the voltage across the port capacitor is a linear function of the generated ramped voltage; comparing a second function of the voltage at a terminal of the electronically controlled switch with a predetermined reference voltage; and responsive to the outcome of the comparison indicating that the second function of the terminal voltage is greater than the predetermined reference voltage, pulling the generated ramp voltage towards a predetermined shutoff voltage.

Abstract: In a network including a controllable device, a method for sending a network management method to the controllable device including asserting a network management command directed to the controllable device and in response to the network management command generating and sending over the network a first number of WOL packets having a predetermined relationship to one another, followed by generating and sending over the network a second number of WOL packets, a predetermined relationship between the second number of WOL packets defining the network management command

Abstract: An MPS generation method, the method constituted of: at a predetermined frequency, alternately outputting a first MPS current pulse for a predetermined first time period and not outputting the first MPS current pulse for a predetermined first off time period; during the first time period, determining the magnitude of a current drawn by an input capacitor of a DC to DC converter; and responsive to the determined input capacitor current magnitude, outputting between the first terminal and the second terminal a second MPS current pulse for a predetermined second time period during the predetermined first off time period.

Abstract: An MPS generation method, the method constituted of: at a predetermined frequency, alternately outputting a first MPS current pulse for a predetermined first time period and not outputting the first MPS current pulse for a predetermined first off time period; during the first time period, determining the magnitude of a current drawn by an input capacitor of a DC to DC converter; and responsive to the determined input capacitor current magnitude, outputting between the first terminal and the second terminal a second MPS current pulse for a predetermined second time period during the predetermined first off time period.

Abstract: A mark and hold system comprising a main power supply, a mark voltage power supply and a detection current source. After detection, and optionally classification, the main power supply is disconnected from the PD and instead the PD is connected to the mark voltage power supply. The detection current source draws current through a port resistance of the PSE and the PD. The voltage across the port resistance is monitored to determine whether the PD is still connected to the port.

Abstract: A reverse power feeding power PSE in electrical communication with a power source and a DPU, the PSE constituted of: a power output terminal; and a control circuitry, the control circuitry arranged to: output at the power output terminal power from the power source, the output power exhibiting a voltage within a predetermined operating range, after a predetermined inrush time period from an initial output time of the power, determine the magnitude of current flowing through the power output terminal, responsive to the determined current magnitude being greater than a predetermined current draw value, cease the power output.

Abstract: A method for monitoring power delivered to a powered device over communication cabling, the method comprising: enabling a first supply power; enabling a second supply power; for the enabled first supply power, providing a first maintain power signature (MPS) functionality arranged to disable the enabled first supply power in the event that the current drawn from the enabled first supply power is less than the first undercurrent threshold; for the enabled second supply power, providing a second maintain power signature (MPS) functionality arranged to disable the enabled second supply power in the event that the current drawn from the enabled second supply power is less than the second undercurrent threshold; receiving an indication that the powered device presents a single powered device interface to both the first and the second PSE; and controlling one of the provided first and second MPS functionality responsive to the received indication.

Abstract: A PoE power utilization method constituted of: detecting a first function of a voltage between a current path node and a current return path node during a first time period and during a second time period, the second time period different than the first time period; sensing a second function of the magnitude of a current flowing through the current path during the second time period; responsive to the detected first time period voltage function, the detected second time period voltage function and the sensed second time period current magnitude function, determining a third function of a resistance seen by the current path; and outputting an indication of the determined resistance function.

Abstract: A PoE system PSE, constituted of: a power source input; a classification functionality arranged to determine the class of a PD; a memory arranged to store thereon the determined class; a timing functionality arranged to output the length of a power interruption to the power source input; and a control circuitry; wherein, responsive to an indication of the timing functionality that the power interruption length is greater than a predetermined time value, the control circuitry is arranged to initiate the class determination of the classification functionality, and wherein, responsive to an indication of the timing functionality that the power interruption length is not greater than the predetermined time value, the control circuitry is arranged to: supply power from the power source input to the PD responsive to the stored determined class; and not initiate the class determination of the classification functionality prior to the power supplying.

Abstract: A powered device interface constituted of: a first and second rectifier bridge, the outputs and returns thereof in electrical communication with each other; and a selection circuit; and a classification current circuit in electrical communication with the output and return of each of the first rectifier bridge and the second rectifier bridge, and further in electrical communication with a first and second input of the first rectifier bridge, wherein the classification current circuit is arranged, responsive to a classification voltage received at one of the first rectifier bridge and the second rectifier bridge, to: in the event that the classification voltage is received at the first rectifier bridge, output a first classification current exhibiting a first magnitude; and in the event that the classification voltage is received at the second rectifier bridge, output a second classification current exhibiting a second magnitude.

Abstract: A power over Ethernet (PoE) connection check method comprising: for a first time period, generating a first detection power over the first set of wires while not generating a second detection power over the second set of wires and obtaining a first indication of a power attribute over the first set of wires; during a second time period, generating the first detection power and generating a second detection power, greater than the first detection power, over the first set of wires; during the second time period, obtaining a second indication of the power attribute over the first set of wires; determining a first difference between the first indication and the second indication; and controlling a first power enable circuit and a second power enable circuit to provide power to the powered device over the first and second sets of wires respectively, responsive to the determined difference.

Abstract: A reverse power feeding PSE in electrical communication with a DPU, the PSE constituted of: a control circuitry; and a detection and classification signal circuitry, arranged to: output a detection signal; output a classification signal; and output an additional signal exhibiting a voltage below an operating range, and wherein the control circuitry is arranged to: responsive to the output first detection signal, detect a valid signature resistance; responsive to the output first classification signal, receive a classification current and determine the class of the DPU; responsive to the output additional signal, detect the absence, or presence, of an off-hook phone; responsive to the detection of the absence of an off-hook phone, and further responsive to the detection of the valid signature resistance, output power exhibiting a voltage within the operating range; and responsive to the detection of the presence of an off-hook phone, not output power.

Abstract: A PSE control circuitry arranged to: control the power source to output a detection signal; responsive to the detection signal, determine the resistance of a signature resistive element; in the event that the determined resistance is within a predetermined range, control a power source to output power to the load; in the event that the determined resistance is outside the predetermined range, prevent the power source from outputting power for a predetermined disconnect time period; detect the amount of power drawn from the power source; in the event that the detected power amount is less than a predetermined minimum power draw value, control the power source to cease output of power for a predetermined power down time period, the predetermined power down time period less than the predetermined disconnect time period; immediately subsequent to both time periods, control the power source to output the detection signal.

Abstract: An integrated limiter and active filter constituted of: an input node; an output node; a transistor coupled between the input node and the output node; a first control circuit coupled to the control terminal of the transistor and arranged to limit the amount of current flowing through the output node to a predetermined value which is responsive to a signal received at a first reference input; a second control circuit coupled to the control terminal of the transistor and arranged to limit the voltage appearing at the output node to a predetermined value which is responsive to a signal received at a second reference input; and a third control circuit coupled to input node and arranged to provide the second reference input, the third control circuit arranged to set the second reference input responsive to the input voltage and to a predetermined maximum allowed output voltage.

Abstract: A reverse power feeding system for supplying power from a plurality of first devices to a second device, a first set of the plurality of first devices each being powered by a first type power source and a second set of the plurality of first devices each being powered by a second type power source different than the first type power source, the system constituted of: a plurality of power paths, each of the plurality of power paths arranged to transfer DC power between a respective one of the plurality of first devices and the second device; and a control circuitry, the control circuitry arranged to adjust the amount of power supplied by each of the second set of the plurality of first devices over the power paths responsive to the total amount of power supplied by the first set of the plurality of first devices over the power paths.

Abstract: A PoE midspan injector constituted of: an Ethernet device side data port; a PD side data port; a plurality of pairs of data wires coupling the Ethernet device and PD side data ports; a power reception port; a pair of first type coils; and a pair of second type coils, each second type coil coupled in series to a respective first type coil thereby forming a coil set, wherein the power reception port is coupled to each wire of a pair of data wire pairs at a respective power node, via a respective coil set, wherein the impedance of the first type coil is greater than the impedance of the second type coil when data is being transmitted at a minimum frequency, and wherein the impedance of the second type coil is greater than the impedance of the first type coil when data is being transmitted at a maximum frequency.