Abstract: A method for transporting Ethernet frame packets assembled from a constant bit rate (CBR) client stream from an ingress network node to an egress network node, each Ethernet frame packet including a payload region having a number of bytes of CBR client data from the CBR client stream determined by a client rate value of the CBR client stream. The method including synchronizing a reference clock signal and a ToD in the ingress network node to a packet-based time distribution mechanism, independently synchronizing a reference clock signal and a ToD in the egress network node to the packet-based time distribution mechanism, for an Ethernet frame packet assembling a presentation time packet including a sequence number and a presentation ToD for the Ethernet frame packet, and transmitting the Ethernet frame packets and the presentation time packet to the egress network node over the packet transport network.

Abstract: A method for transporting Ethernet frame packets assembled from a constant bit rate (CBR) client stream from an ingress network node to an egress network node, each Ethernet frame packet including a payload region having a number of bytes of CBR client data from the CBR client stream determined by a client rate value of the CBR client stream. The method including synchronizing a reference clock signal and a ToD in the ingress network node to a packet-based time distribution mechanism, independently synchronizing a reference clock signal and a ToD in the egress network node to the packet-based time distribution mechanism, for an Ethernet frame packet assembling a presentation time packet including a sequence number and a presentation ToD for the Ethernet frame packet, and transmitting the Ethernet frame packets and the presentation time packet to the egress network node over the packet transport network.

Abstract: A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillators, a second phase acquisition circuit coupled to the input for the reference clock source and to the second crystal oscillator, a first DPLL coupled to the first phase acquisition circuit, a crystal oscillator variation estimator coupled to the first DPLL, a second DPLL coupled to the second phase acquisition circuit and including a phase-frequency detector having a input coupled to the second phase acquisition circuit, a loop filter, a frequency subtractor having an input coupled to the loop filter and an input coupled to the crystal oscillator variation estimator, and a DCO coupled to the frequency subtractor and driving an input of the phase-frequency detector.

Abstract: Substrates configured to route electrical signals may include a first dielectric material and an electrically conductive material located on a first side of the first dielectric material. A second dielectric material may be located on a second, opposite side of the first dielectric material. A series of voids may be defined by the second dielectric material extending from the first dielectric material at least partially through the second dielectric material. Footprints of at least some of the voids of the series of voids may at least partially laterally overlap with the electrically conductive material.

Abstract: A method for transferring first and second encoded client clock signals over a carrier clock domain between integrated circuits, including in a first integrated circuit encoding a phase change of the first client clock signal from a last recorded phase onto the carrier clock signal in first bit positions, encoding a phase change of the second client clock signal from a last recorded phase onto the carrier clock signal in second bit positions different from the first bit positions, and transmitting the carrier clock signal with the encoded phases of the first client clock signal and the second client clock signal over a single wire from the first integrated circuit to a second integrated circuit.

Abstract: In a receiver a method for extracting first and second signals from a single signal includes receiving the single signal, generating a recovered first signal by extracting and phase locking the first signal with respect to the phase of a local clock, decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time, generating a phase difference between the first signal and the second signal as a function of data representing phase difference from a current decode frame time and data representing an encoded phase difference from an immediately prior decode frame time, subtracting the generated phase difference from the phase of the recovered first signal, and generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.

Abstract: A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate fS for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate fsamp, the first clock rate fS being N times greater than the second clock rate fsamp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate fsamp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.

Abstract: A clock recovery device recovers frequency and timing information from an incoming packet stream over asynchronous packet networks. A phase locked loop (PLL) block has predefined states and includes a type II PLL. One of the states involves type II PLL operation. A state machine controller for controls the transition between the predefined states in response to changes in the incoming packet stream. A controlled oscillator is responsive to the PLL block to generate an output signal.

Abstract: An acoustic signal delay measurement apparatus constituted of: an acoustic signal input terminal; an acoustic signal output terminal; at least one echo input terminal; an adjustable tapped delay line exhibiting a plurality of taps, a first end of the tapped delay line coupled to the acoustic signal input terminal, each of the taps exhibiting a respective predetermined delay; a processor, an output of the processor coupled to a control input of the adjustable tapped delay line; and a plurality of adaptive filters, a first input of each of the plurality of adaptive filters coupled to a respective one of the at least one echo input terminal, a second input of each of the plurality of adaptive filters coupled to a respective one of the plurality of taps and an output of each of the plurality of adaptive filters coupled to a respective input of the processor, wherein the processor is arranged to determine a system delay responsive to: the amount of time it takes for one of the plurality of adaptive filters to conv

Abstract: A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate fS for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate fsamp, the first clock rate fS being N times greater than the second clock rate fsamp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate fsamp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.

Abstract: A clock recovery device recovers a master clock over a packet network from incoming synchronization packets. A frequency locked loop generates a control input to a controlled oscillator, which generates an output clock. The frequency locked loop is responsive to pure offset information obtained from the incoming synchronization packets. A transient phase adjuster extracts information from the incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of the control input and to provide a phase adjustment input to the frequency locked loop. A secondary phase path is selectable in response to de-activation of the transient phase adjuster to provide a phase correction to the control input derived from said pure offset information when the transient phase adjuster is inactive.

Abstract: A clock synthesizer for synthesizing an output clock locked to a selected reference clock input has a pair of phase locked loops locked to respective reference clock inputs first generating first and second frequencies. One of the frequencies is selected to control a controlled oscillator for generating an output clock. The frequency offset between the first and second frequencies at the time of switching is stored and added to the frequency controlling the controlled oscillator.

Abstract: A compensation circuit for an oven-controlled crystal oscillator serving as a reference for a phase-locked loop in holdover mode is disclosed. A non-linear function module generates a modified aging signal that is a non-linear function of an aging signal. A first Kalman filter generates an estimate of the frequency drift of the crystal oscillator based on the temperature signal. A second Kalman filter generates an estimate of the frequency drift based on the modified aging signal. A combining and comparing module combines the estimates generated by the first and second Kalman filters and compares the estimates with detected frequency drift to produce an error signal to update the Kalman filters. In holdover mode the Kalman filters generate an error signal to correct the oscillator frequency based on updates obtained during operation of the phase-locked loop in normal mode.

Abstract: A method of compensating for integral nonlinear interpolation (INL) distortion in a clock synthesizer driven by a system clock running at a frequency fsys, involves introducing a selected nominal analog delay I*dt with an actual delay of I*dt+? at the output of the a first path with a digital controlled oscillator (DCO) and a digital-to-time converter (DTC) and a nominal digital delay I*D with an actual delay of I*D+? at the input of a second path with a DCO and a DTC that offsets the actual analog delay in the first path, adjusting the contents x(k) of a compensation module in the second path to align the output pulses of the first and second paths for different values of k, where k represents an interpolation point, iteratively repeating the two preceding steps for all N values of I, and averaging the contents x(k) of the compensation module to derive the compensation values to be applied to a one of the DTCs to correct for INL distortion.

Abstract: To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

Abstract: A method for reducing the jitter introduced into a digital signal by a non-linear processing element involves applying an input word representing the digital signal to a first signal path comprising a first non-linear processing element, and a complementary version of the input word to a second signal path comprising a second non-linear processing element. A common mode dither signal is injected into each signal path upstream of the non-linear processing elements. The outputs of the non-linear processing elements are combined to produce a common output with the common mode dither signal removed.

Abstract: A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).

Abstract: A time-to-digital converter (TDC) measures a time interval ?TTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=?TTot?mTNOR to obtain a value for the time interval ?TTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.

Abstract: A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.

Abstract: A slave device for exchanging data with a master device over a serial interface sends data to the master device upon receipt of a command from the master device. A controller responsive to a command byte in a receive register commences transmission of data in the transmit register under the control of a clock signal prior to reception of a complete command.