Abstract: A system and method for the identification of system jitter in a circuit are provided. The apparatus may include a delay line circuit including a plurality of combinatorial logic circuits arranged sequentially including a first combinatorial logic circuit and a second combinatorial logic circuit having a plurality of inputs and outputs, a pulse generation circuit to output a generated pulse to a first input of the first combinatorial logic circuit, capture circuit to capture a binary state of at least one of the plurality of outputs. The first and the second combinatorial logic circuits may have a logic propagation path from a first input to a first output. The logic propagation path may have a logic propagation delay between the input pulse and the output pulse determined by a logic value applied to a second input.

Abstract: The system may speed up reduced instruction set computing/single instruction, multiple data (RISCV/SIMD) vector processing (VP) by adding a register circuit for an additional vector register file for a total of two VRF registers. One of the VRF registers may be used for data transfers to and from memory, and the other VRF register may be used for arithmetic logic unit (ALU) operands. The VRFs may be switched alternatively to perform the data transfers and operands.

Abstract: A method may create RTL for a circuit design utilizing DSP blocks by receiving a software program comprising a multiplication statement to multiply a first number by a second number, the first number having a first data type and a first bit width, the second number having a second data type and a second bit width; determining a number of DSP blocks for implementing the statement based at least on the first bit width, the second bit width, a first DSP bit width corresponding to a bit width of a first operand of the DSP blocks, and a second DSP bit width corresponding to a bit width of a second operand of the DSP blocks, wherein the number of DSP blocks is two or more; and generating RTL for the statement, the RTL comprises a plurality of distinct portions corresponding to each of the two or more DSP blocks.

Abstract: A memory cell comprises NMOS and PMOS transistors and voltage-controlled impedance components (VCICs). A first NMOS transistor and a first PMOS transistor form a first inverter. A second NMOS transistor and a second PMOS transistor form a second inverter. The first inverter and the second inverter are electrically connected to one another to form cross-coupled inverters, wherein an input of the first inverter is coupled to an output of the second inverter and an output of the first inverter is coupled to an input of the second inverter. A first VCIC is electrically connected between the output of the first inverter and the input of the second inverter. A second VCIC is electrically connected between the input of the first inverter and the output of the second inverter. An impedance of each VCIC varies according to one or more control voltages applied to the respective VCIC.

Abstract: Systems and methods for averaging a digital phase locked loop output frequency to calculate a preset value for use in the event of a link loss are disclosed. The method may include reading a fractional portion of an output of a digital phase locked loop (DPLL), calculating an integer portion of the output of the DPLL, and accumulating a predetermined number of samples of the fractional portion and the integer portion of the output of the DPLL. The method may include computing an average value of an output frequency of the DPLL over the predetermined number of samples, extracting a fractional portion and an integer portion of the average value of the output frequency of the DPLL, and loading the fractional portion and the integer portion of the average value of the output frequency of the DPLL as preset values in a fractional-N phase locked loop.

Abstract: Systems for identifying power coupling effects that include a circuit, at least one processor, and a memory. The circuit may include a power delivery network (PDN) and a plurality of circuit blocks. The memory may store instructions that, when executed by the at least one processor, cause the at least one processor to perform the following operations: extract power structure parameters of the circuit; generate, based on the parameters, a PDN model, said PDN model including the PDN and the plurality of circuit blocks; test, using the PDN model, the plurality of circuit blocks; and identify, based on the testing, a power coupling effect within the PDN.

Abstract: A method for providing on-chip instrumentation comprises receiving a source code which specifies a design to be programmed into a field programmable gate array (FPGA); generating a high-level instrumentation specification derived from the source code and which indicates levels of components in the FPGA to instrument; generating a low-level instrumentation specification derived from the high-level instrumentation specification and which identifies specific components in the FPGA to instrument; receiving a dumpfile that includes data regarding the specific ports, the specific signals, and the specific operating parameters derived from data received from the FPGA; generating a waveform update file that includes data from the FPGA regarding the specific ports, the specific signals, and the specific operating parameters, the data generated in a format for viewing in a waveform viewer; and generating triggering data to determine a plurality of times at which the specific signals are sampled.

Abstract: A memory cell may include a word write line, a first bit line, a first storage node, a second storage node, a first passgate transistor, and a read circuit. A gate of the first passgate transistor may be electrically connected to the word write line. A source of the first passgate transistor may be electrically connected to the first bit line. A drain of the first passgate transistor may be electrically connected to one of the first and second storage nodes. The read circuit may include a word read line, a first read transistor, and a second read transistor. A gate of the first read transistor may be electrically connected to the first storage node. A gate of the second read transistor may be electrically connected to the word read line. A drain of the first read transistor may be electrically connected to the second read transistor.

Abstract: System and method for updating a target device. Firmware information associated with the target device may be detected. A GUI including actionable items may be presented on a display. User selections for the actionable items may be received. A configuration table for the target device may be built based on the user selections. The target device may be updated based on the configuration table and the firmware information.

Abstract: One or more examples relate to a complementary metal-oxide-semiconductor (CMOS) device. The CMOS device includes a CMOS pass gate circuit, a control circuit, and a bootstrap circuit. The CMOS pass gate circuit includes an n-channel transistor and a p-channel transistor. The control circuit may activate and deactivate the CMOS pass gate circuit. The bootstrap circuit may be electrically connected between the CMOS pass gate circuit and the control circuit. The bootstrap circuit may increase a first drive gain of the n-channel transistor and a second drive gain of the p-channel transistor.

Abstract: A memory cell comprises a plurality of n-type metal oxide semiconductor (NMOS) transistors and a plurality of p-type metal oxide semiconductor (PMOS) transistors. First and second NMOS transistors are electrically connected to one another in a cross-coupled configuration. First and second PMOS transistors are electrically connected to one another in a cross-coupled configuration. Third and fourth NMOS transistors are electrically connected to the first and second NMOS transistors in a cascode configuration. Third and fourth PMOS transistors are electrically connected to the first and second PMOS transistors in a cascode configuration. A fifth PMOS transistor includes a drain, a gate, and a source, wherein the drain is electrically connected to a gate of the second PMOS transistor and a drain of the first PMOS transistor, and the source is electrically connected to a gate of the first PMOS transistor and a drain of the second PMOS transistor.

Abstract: A non-transitory computer readable memory (CRM) is provided comprising instructions that, when executed on a processor, receive a request message from a source code editor including a location in an HLS design file and an autocompletion request, the HLS design file including at least one HLS command, identify zero or more tokens for the request, and generate a response message.

Abstract: A non-transitory computer readable medium is provided comprising instructions that when executed on a processor load a software program into a software debugger for execution on an emulated processor representing a processor portion of a system on chip (SoC), load a hardware design into a hardware simulator representing a programmable gate array portion of the SoC, coordinate execution of software debugger and hardware simulator to simulate operation of the SoC, communicate data between the software debugger and the hardware simulator, and display computed results and current values.

Abstract: A device and method is provided with a first portion of the device in communication via a data line with a second portion of the device, an retiming circuit to receive a first clock from the first portion of the device and a second clock from the second portion of the device; and introduce a delay value in the second clock to generate a delayed clock; and a validation circuit to receive a data value arriving at the first portion of the device; capture a first sample of the data value sampled with the first clock; capture a second sample of the data value sampled with the delayed clock; and compare the first sample with the second sample.

Abstract: A circuit, and method for using same comprising, a first intermediate memory communicatively coupled with a vector processor and a RAM, wherein the vector processor is communicatively coupled with the RAM, an address sequence memory to store non-linear RAM addresses corresponding to linear locations in the first intermediate memory, a data sequencer to read a first frame of data from the RAM to the first intermediate memory based on addresses stored in the address sequence memory, and the first intermediate memory to provide a linearized frame of data to the vector processor to execute a vector instruction

Abstract: A ReRAM memory array includes ReRAM memory cells and a select circuit having first and second series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for programming, the bit line coupled to the ReRAM memory cell(s) to be programmed is biased at a first voltage potential and the source line coupled to the ReRAM memory cell(s) to be programmed is biased at a second voltage potential less than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to program the ReRAM device. The gates of first and second series-connected select transistors of ReRAM memory cell(s) to be programmed are supplied with positive voltage pulses. The gates of second series-connected select transistors of respective ReRAM memory cell(s) unselected for programming are supplied with a voltage potential insufficient to turn them on.

Abstract: Methods and systems for tamper detection based on power network electrical characteristic by storing a reference electrical signature of a power distribution network comprising the integrated circuit, generating in the integrated circuit a current stimulus waveform by sigma-delta based noise shaping, and providing the waveform to the power distribution network comprising the integrated circuit, sampling the power distribution network with a voltage-to-digital converter in the integrated circuit and estimating based at least partially on the sampled power distribution network a response electrical signature of the power distribution network responsive to the stimulus waveform, comparing on the integrated circuit the estimated response electrical signature and the reference electrical signature, and triggering by the integrated circuit a penalty based on a comparison of the response electrical signature and the reference electrical signature.

Abstract: A ReRAM memory array includes ReRAM memory cells having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors of the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors of the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.

Abstract: A method may create RTL for a circuit design utilizing DSP blocks by receiving a software program comprising a multiplication statement to multiply a first number by a second number, the first number having a first data type and a first bit width, the second number having a second data type and a second bit width; determining a number of DSP blocks for implementing the statement based at least on the first bit width, the second bit width, a first DSP bit width corresponding to a bit width of a first operand of the DSP blocks, and a second DSP bit width corresponding to a bit width of a second operand of the DSP blocks, wherein the number of DSP blocks is two or more; and generating RTL for the statement, the RTL comprises a plurality of distinct portions corresponding to each of the two or more DSP blocks.

Abstract: A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.