Abstract: A method and system are provided for drift compensation, providing a live data approach to sampler offset calibration, such as for voltage and/or temperature (VT) drift. A serializer/deserializer (SerDes) system includes a SerDes receiver and receiver logic, the receiver logic including a forward error correction (FEC) module. A drift compensation device, or drift compensation engine, receives live error corrections from the FEC module based on FEC operations performed on live traffic passing through the SerDes receiver. A drift compensation command is provided to a data sampler in the SerDes receiver, to adjust a sampling voltage of the data sampler. When the system includes a plurality of data samplers, the drift compensation device determines the data sampler with which an error correction is associated. The drift compensation command can be sent after a threshold criterion is satisfied, such as completion of a statistics collection period, or a threshold number of corrections.

Abstract: Systems and methods are provided for transparently transmitting multiple constant bitrate (CBR) data streams over a packet network with reduced delay. Example embodiments provide packetizers and depacketizers for multiplexing and demultiplexing multiple common public radio interface (CPRI) data streams for transport between remote units and baseband units over packet networks. The systems and methods disclosed herein use time-division-multiplexing to map multiple CBR clients directly into a packet such that each CBR client can be recovered at the destination with its original clock and with information that allows its residence time in the packet domain to be calculated. The systems and methods disclosed herein allow packet based networks, such as the existing Packet Transport Network (PTN), to be used for C-RAN fronthaul applications with strict end-to-end delay requirements.

Abstract: A method and system for transferring NVMe data over a network comprises using a discrete buffer memory device to generate a write command from an NVMe-over-RDMA write command request, store the user data from a client host of the network, and send an interrupt signal to a NVMe storage device of the network. The NVMe storage device retrieves the write command from the discrete buffer memory device and performs a direct memory access transfer of the stored user data from the discrete buffer memory device to the NVMe storage device. The discrete buffer memory device comprises a controller and a random access memory for generating commands and storing the commands in a submission queue of the random access memory. The controller can clear commands from the submission queue based on completion commands received in a completion queue of the random access memory.

Abstract: A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.

Abstract: The present disclosure relates to a reconfigurable multicore inductor capacitor (LC) oscillator comprising a plurality of oscillator cores. The oscillator may be configured at run-time, at manufacturing, or at production, which may allow for the tailoring of operating characteristics of the oscillator, such as phase noise, electromagnetic interference, or power consumption, for a specific application after production. The cores are coupled through an interconnect network to a common electrical signal output. A subset of the cores may be selectively enabled while the remainder of the cores is disabled. The ability to enable only a subset of the cores allows the total number of enabled cores to be reconfigurable. Furthermore, the direction in which oscillation current flows through the inductor of the cores may be configured. Reconfiguring the number of enabled cores and/or the oscillation current direction in the cores allow operating characteristics of the oscillator to be tailored after production.

Abstract: A frame delineation method for a generic framing procedure (GFP) that includes: searching a serial data stream comprising GFP frames, octet by octet, to identify an eight octet sequence; and delineating GFP frames from the serial data stream in response to determining that a first group of four octets of the identified eight octet sequence comprises a valid Core Header, and in response to determining that a second group of four octets of the identified eight octet sequence comprises one of a valid Core Header and a valid descrambled Type Header.

Abstract: A system for implementing variable T BCH encoders includes: a polynomial multiplier for multiplying a message polynomial by a difference polynomial to achieve a first value, wherein the message polynomial comprises data bits as coefficients and the difference polynomial comprises minimal polynomials that are present in a T error correcting code and are absent from a T??T error correcting BCH code; a shifter/zero-padder coupled with the BCH encoder, the shifter/zero-padder for multiplying the first value by xN-{tilde over (K)} to achieve a second value; a BCH encoder coupled with the polynomial multiplier, the BCH encoder for dividing the second value by a generator polynomial of the T error correcting BCH code and calculating a remainder based on the dividing to achieve a third value; and a polynomial divider for dividing the third value by the difference polynomial to achieve a fourth value comprising parity of the T??T error correcting BCH code.

Abstract: A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders connected to the master SAS expander. Each slave expander has a distinct SAS address. The slave expanders are not directly connected to one another and communicate through the master expander. The SAS switch has a pair of SAS wide ports each having a multitude of SAS links each associated with one of the slave expanders. The slave expanders are configured to route SAS traffic in accordance with routing tables established by the master SAS expander. The master SAS expander is not directly connected to either of the SAS wide ports.

Abstract: Methods, devices, and systems relating to Serial Attached SCSI (SAS) storage interconnect technology are provided. An SAS serial connection is established between an SAS initiator and an SAS expander over a physical link for communications between the SAS initiator and a plurality of target devices. The plurality of target devices is in communication with the SAS expander. SAS packets associated with each of the plurality of target devices are dynamically multiplexed and transmitted over the single SAS serial connection. Each SAS packet comprises one or more information bits indicating the target device with which the SAS packet is associated. The dynamically multiplexed SAS packets transmitted over the SAS connection may comprise SAS packets associated with at least two target devices having different maximum physical link rates. A result may be improved bandwidth utilization of the physical link when legacy SAS target devices with slower physical link rates are utilized.

Abstract: Methods, devices and systems are provided for making a shingled magnetic recording (SMR) hard disk drive operate with similar random access characteristics of a conventional hard drive despite the SMR disk having strict sequential write requirements. A virtual space manager manages a virtual address space, which is visible to a host system, and maps virtual addresses to logical addresses on the SMR disk. A logical space manager controls the placement of data on the SMR disk and ensures that writes to the disk comply with the sequential write requirements. The disk is subdivided into a plurality of stripes each comprising one or more blocks. When a block located within a stripe is to be rewritten with new data, the entire stripe is read from the SMR disk into a memory of the system, the stripe is modified in the memory to replace the previous data stored in the block with the new data, and the modified stripe is written to a new, next available stripe on the disk.

Abstract: An apparatus and method for port mirroring in a plurality of Peripheral Component Interconnect express (PCIe) interfaces includes, for each PCIe interface, output transmission ports for transmitting data to a central processing unit (CPU), receiving input ports for receiving data from the CPU, port-mirror-in (PM_IN) ports, and port-mirror-out (PM_OUT) ports provided in a PHY layer instance. The PM_OUT ports of each PHY layer instance is coupled to the PM_IN ports of a next PHY layer instance such that the PHY layer instances of the plurality of PCIe interfaces are connected in a ring bus architecture for mirroring one or more ports of the output transmission ports or the receiving input ports of a first active PHY layer instance can be mirrored to output transmission ports of a second PHY layer instance.

Abstract: The present disclosure relates to a system and method of encrypting and decrypting Optical Transport Network (OTN) payload content. A transmitter of the system includes a series of ordered encryption keys and a counter for generating an initialization vector to be combined with one of the encryption keys for encrypting the OTN payload content. A receiver of the system includes a series of ordered decryption keys and a counter for generating an initialization vector to be combined with one of the decryption keys for decrypting the encrypted OTN payload content. The system synchronizes switching, at the transmitter and the receiver, the encryption and decryption keys to the next keys in each series. The system also synchronizes the counters for generating the same initialization vector at the transmitter and the receiver.

Abstract: The present disclosure provides a method and system for dynamically migrating a port in a PCIe switch. The PCIe switch comprises emulated P2P bridges stored in a memory and a processor to load the emulated P2P bridge address range values from the memory to a routing table. The processor can configure the routing table so that the P2P bridges can be remapped to various physical ports of the switch. Therefore, a device connected to a physical port may be migrated from one host to another, via the operations of the processor.

Abstract: A method and system are provided for transmitting SATA (serial advanced technology attachment) information. In an implementation, SATA commands are passed to an expander, rather than SCSI (Small Computer System Interface) commands. In an example implementation, SATA protocol elements are encapsulated into SAS (Serial Attached SCSI)-like frames and transmitted using the SSP (Serial SCSI protocol) and using SSP hardware.

Abstract: A power-saving method and circuit in a data processing device comprising a data buffer. Data transfer commands associated with a data source and a data destination are received at the data processing device. The data transfer commands are accumulated until an amount of data associated with the read commands is greater than a predefined threshold. When the amount of data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a power saving mode. When the amount of data is at least the predefined threshold, the data buffer is signaled to exit the power saving mode following a predetermined delay. Processing of the commands and data in respective pipelines is monitored to time exiting of the buffer from the power saving mode for arrival of the data. Power saving mode use and thus power saving are optimized.

Abstract: A solid-state storage device (SSD) controller is provided for use with an SSD. The SSD includes a plurality of memory cells, such as non-volatile memory (NVM) cells. The SSD controller comprises a processor and a memory storing statements and instructions for execution by the processor to perform a method of configuring the memory cells. In a dynamic configuration implementation in which at least a subset of the NVM cells are configured in a first bit retention mode, the method includes: monitoring data activity in relation to the SSD; and dynamically reconfiguring the subset of the NVM cells in a second bit retention mode based on the monitored data activity, such as whether data traffic comprises a majority of read activity or write activity. In a static configuration implementation, the method includes receiving at least one performance characteristic for the NVM cells; and configuring the subset of the NVM cells in a first bit retention mode based on the received at least one performance characteristic.

Abstract: An apparatus for monitoring operation of a design under test (DUT) includes an incoming clock edge input; an outgoing clock edge input; an enable input; a protocol input; an upstream clocking input; and a downstream clocking input. The apparatus also includes a memory in communication with the inputs for storing values from the inputs, and a processor in communication with the memory and the inputs, the processor programmed to determine spurious and missing active clock edges sent from the monitored clock gate. The apparatus also includes a clock categorization output to output the determination of the active clock edges from the monitored clock gate as missing or spurious.

Abstract: A transmit datapath and a method for timestamping packets. The datapath comprises a timestamp unit located along a packet bus. The timestamp unit is configured to timestamp a packet with its predicted departure time onto a link, the predicted departure time based on an actual departure time of a preceding packet and the lengths of all intervening packets, when the packet bus has been continuously full of the intervening packets. The method comprises determining the predicted departure time of a packet based on an actual departure time of a preceding packet and the lengths of all intervening packets, minimizing the inter-frame gaps between the intervening packets, and timestamping the packet with the predicted departure time. The timestamp method may be a 1-step timestamp method. A packet may be timestamped with its predicted departure time upstream from where the packet is protected. The protection may be MACSec protection.

Abstract: A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders connected to the master SAS expander. Each slave expander has a distinct SAS address. The slave expanders are not directly connected to one another and communicate through the master expander. The SAS switch has a pair of SAS wide ports each having a multitude of SAS links each associated with one of the slave expanders. The slave expanders are configured to route SAS traffic in accordance with routing tables established by the master SAS expander. The master SAS expander is not directly connected to either of the SAS wide ports.

Abstract: Methods and apparatus are provided for controlling one or more memory devices connected to an input output (IO) circuit through a serial peripheral interface (SPI), to make any device which is in execute in place (XIP) mode exit XIP mode. An example method comprises driving an initial signal from the IO circuit onto the data pins for a first plurality of clock cycles, the initial signal causing any memory device not in XIP mode to treat subsequent signals as a dummy read, disabling a driving function of the IO circuit prior to a negative edge of a last one of the first plurality of clock cycles, stopping generation of clock signals for a transition waiting period after the first plurality of clock cycles, and activating a weak pull-up of the IO circuit to apply logic high on all of the data pins for a second plurality of clock cycles.