Abstract: A method and apparatus includes receiving at a sink node a path signal frame and a modified set of idle character 64B/66B blocks. The path signal frame includes encoded client data signal 64B/66B blocks, path overhead 64B/66B data blocks and a control 64B/66B block. The link bit rate is measured. The number of idle character 64B/66B blocks is determined. The data blocks of the CBR client signal are extracted from the encoded client data signal 64B/66B blocks and the CBR client signal is regenerated from the extracted data blocks. A bit rate of the CBR client signal is determined using the measured link bit rate and the number of idle character 64B/66B blocks. The rate of a CBR signal clock is adjusted for transmitting the CBR client signal at the determined bit rate.

Abstract: A source node for rate adapting a constant bit rate client signal into a signal stream in a 64B/66B-block telecom signal communication link includes a GMP engine; a FIFO buffer coupled to receive a 64B/66B encoded client data stream; a clock rate measuring circuit; a source of 64B/66B path overhead blocks; a source of 64B/66B pad blocks; a source of 64B/66B idle blocks; a multiplexer; and a multiplexer controller. A control 64B/66B block is encoded into an ordered set block-designator and a count of data blocks to be sent in a next path signal frame is encoded into a plurality of path overhead 64B/66B data blocks. The multiplexer controller is responsive to a count of data blocks to be sent in a next path signal frame from a previous GMP window frame to selectively pass data to a data output so as to fill a GMP window frame.

Abstract: A source node for rate adapting a constant bit rate client signal into a signal stream in a 64B/66B-block telecom signal communication link includes a GMP engine; a FIFO buffer coupled to receive a 64B/66B encoded client data stream; a clock rate measuring circuit; a source of 64B/66B path overhead blocks; a source of 64B/66B pad blocks; a source of 64B/66B idle blocks; a multiplexer; and a multiplexer controller. A control 64B/66B block is encoded into an ordered set block-designator and a count of data blocks to be sent in a next path signal frame is encoded into a plurality of path overhead 64B/66B data blocks. The multiplexer controller is responsive to a count of data blocks to be sent in a next path signal frame from a previous GMP window frame to selectively pass data to a data output so as to fill a GMP window frame.

Abstract: A method for rate adapting a constant bit rate (CBR) client signal into a signal stream in a telecom signal communication link includes at a source node encoding into a control block a control block header, and an ordered set block-designator, encoding into a plurality of path overhead data blocks a data block header and a count of data blocks to be encoded in a signal block, encoding into each of a plurality of signal blocks a data block header, the data blocks from the CBR signal equal to the count and pad blocks, assembling the blocks into a path signal frame, appending a set of idle character blocks following the end of the path signal frame to match a link bit rate of a first link segment, and transmitting the path signal frame and idle character blocks into the first link segment at the link bit rate.

Abstract: The disclosure relates generally to improvements in caching operations in storage controllers, including caching operations utilizing direct memory access (DMA) systems, and related devices. Rather than the firmware running on the processor of the storage controller having to traverse a dirty cache sector bitmap and manipulate an original scatter-gather (SG) list in order to generate the two separate SG lists, namely one for the cache and one for the storage device, these operations are offloaded onto new specialized hardware referred to herein as a smart DMA engine in order to free up the processor of the storage controller.

Abstract: A setup test method for scheduled networks, the method constituted of: transmitting a frame to at least one network switch; responsive to the transmitted frame arriving at a first time gate of the at least one network switch, timestamping the transmitted frame with a first time stamp; responsive to the transmitted frame traversing a second time gate of the at least one network switch, additionally timestamping the transmitted frame with a second time stamp; reading the first time stamp; responsive to the read first time stamp, determining the time of arrival of the transmitted frame at the first time gate; reading the second time stamp; and responsive to the read first time stamp, determining the time of traversal of the transmitted frame through the second time gate.

Abstract: A PHY constituted of: a clock arranged to generate a time signal indicative of the current time; and an egress stamp functionality arranged to: receive a data packet on the egress side, extract data from a predetermined section of the received data packet, and responsive to the extracted data, perform one of a plurality of predetermined timestamp operations, the plurality of predetermined timestamp operations comprising: generating a timestamp signal responsive to the generated time signal; not generating a timestamp signal; or modifying a timestamp written in the received data packet.

Abstract: A method for rate adapting a constant bit rate (CBR) client signal into a signal stream in a telecom signal communication link includes at a source node encoding into a control block a control block header, and an ordered set block-designator, encoding into a plurality of path overhead data blocks a data block header and a count of data blocks to be encoded in a signal block, encoding into each of a plurality of signal blocks a data block header, the data blocks from the CBR signal equal to the count and pad blocks, assembling the blocks into a path signal frame, appending a set of idle character blocks following the end of the path signal frame to match a link bit rate of a first link segment, and transmitting the path signal frame and idle character blocks into the first link segment at the link bit rate.

Abstract: A multimode, multicore inductor-capacitor (LC) oscillator having an increased oscillation frequency tuning range, and related method, are provided. The oscillation frequency tuning range of existing oscillators is limited. LC oscillators are known to have very low phase noise but a narrow frequency tuning range. The present oscillator has at least two LC oscillator cores and is capable of operating in multiple different modes of oscillation thereby increasing its overall oscillation frequency tuning range. A set of programmable amplifier pairs is used to force particular relative oscillation phases at the nodes of the multiple cores of the oscillator to realize one or more additional modes of oscillation for the oscillator. The additional oscillation mode increases the frequency tuning range of the oscillator.

Abstract: A method and system are provided for error correction. After row encoding and column encoding, additional codeword data (ACD) and modified parity (P?) may be concurrently created, for each of a plurality of modified column codewords (CCW?), by multiplying initial calculated parity P by a generator matrix G. Each CCW? may include an ACD portion and a P? portion such that each bit in the P? portion of a selected CCW? is present in the ACD portion for one of the other CCW?. In contrast to known approaches, the method and system may provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords, each bit in the modified parity in one modified codeword is present in another codeword.

Abstract: A system and method for controlling the performance of one or more target devices. A connection request for a target device of a plurality of target devices is received at a serial attached SCSI (SAS) Expander from an SAS initiator device, wherein a maximum performance availability value is associated with the target device. If the current performance availability value of the target device indicates that the target device does have availability to service the connection request, the connection request from the SAS initiator device is accepted and a connection is established between the SAS initiator device and the target device. Alternatively, if the current performance availability value of the target device indicates that the target device does not have availability to service the connection request, the connection request from the SAS initiator device is rejected and a connection is not established between the SAS initiator device and the target device.

Abstract: Various transmission systems may benefit from techniques to improve the quality of the transmission. For example, certain full duplex transmission systems may include a virtual hybrid coupler. A circuit can include a first feedback resistor. The circuit can also include a second feedback resistor coupled to the first feedback resistor. The circuit can further include a first set of M transistors coupled to the first feedback resistor. The circuit can additionally include a second set of N transistors coupled to the second feedback resistor and to the first set of M transistors. The circuit can be configured to cancel a transmitted signal at a receiver input based on a ratio of resistance values of the first feedback resistor and the second feedback resistor, and based on a ratio of M to N.

Abstract: The disclosure relates generally to improvements in caching operations in storage controllers, including caching operations utilizing direct memory access (DMA) systems, and related devices. Rather than the firmware running on the processor of the storage controller having to traverse a dirty cache sector bitmap and manipulate an original scatter-gather (SG) list in order to generate the two separate SG lists, namely one for the cache and one for the storage device, these operations are offloaded onto new specialized hardware referred to herein as a smart DMA engine in order to free up the processor of the storage controller.

Abstract: A system and method for block-code transcoding. An input signal is analyzed to determine if the input signal includes multiple control words, multiple data words and a single control word or only data words. If the input signal comprises multiple control words, the method includes, generating a control word location map and mapping the control codes and any data words to a block-code encoded transmission signal. If the input signal comprises a single control word and multiple data words, the method includes, generating a control word location address indicating a location of the single control word and mapping the control code and the multiple data words to a block-code encoded transmission signal. If the input signal comprises only data words, the method includes, mapping the data words sequentially into the block-code encoded transmission signal.

Abstract: A system and method for controlling the performance of one or more target devices. A connection request for a target device of a plurality of target devices is received at a serial attached SCSI (SAS) Expander from an SAS initiator device, wherein a maximum performance availability value is associated with the target device. If the current performance availability value of the target device indicates that the target device does have availability to service the connection request, the connection request from the SAS initiator device is accepted and a connection is established between the SAS initiator device and the target device. Alternatively, if the current performance availability value of the target device indicates that the target device does not have availability to service the connection request, the connection request from the SAS initiator device is rejected and a connection is not established between the SAS initiator device and the target device.

Abstract: A system and method for decision feedback equalizer (DFE) tap adaptation. An input signal is received at a DFE of a receiver, wherein the input signal comprises a serial bit stream of encoded symbols. Data samples and error samples are taken from the input signal and the data samples and the error samples are aligned establish a plurality of pairs of data samples and error samples, wherein the data sample and error sample of each of the plurality of pairs of data samples and error samples are from locations in the serial bit stream of encoded symbols that are known to be uncorrelated with each other. The DFE tap weights are then adjusted based upon the plurality of pairs of data samples and error samples.

Abstract: A system and method for block-code transcoding. An input signal is analyzed to determine if the input signal includes multiple control words, multiple data words and a single control word or only data words. If the input signal comprises multiple control words, the method includes, generating a control word location map and mapping the control codes and any data words to a block-code encoded transmission signal. If the input signal comprises a single control word and multiple data words, the method includes, generating a control word location address indicating a location of the single control word and mapping the control code and the multiple data words to a block-code encoded transmission signal. If the input signal comprises only data words, the method includes, mapping the data words sequentially into the block-code encoded transmission signal.

Abstract: A system and method for block-code transcoding. An input signal is analyzed to determine if the input signal comprises multiple data words and multiple control words, multiple data words and a single control word or multiple data words only. If the input signal comprises multiple control words, the method includes, generating a control word location map and mapping the control codes and data words to a block-code encoded transmission signal. If the input signal comprises a single control word, the method includes, generating a control word location address indicating a location of the single control word and mapping the control word and the data words to a block-code encoded transmission signal. If the input signal comprises multiple data words only, the method includes, mapping the multiple data words sequentially into the block-code encoded transmission signal.

Abstract: Various transmission systems may benefit from techniques to improve the quality of the transmission. For example, certain full duplex transmission systems may include a virtual hybrid coupler. A circuit can include a first feedback resistor. The circuit can also include a second feedback resistor coupled to the first feedback resistor. The circuit can further include a first set of M transistors coupled to the first feedback resistor. The circuit can additionally include a second set of N transistors coupled to the second feedback resistor and to the first set of M transistors. The circuit can be configured to cancel a transmitted signal at a receiver input based on a ratio of resistance values of the first feedback resistor and the second feedback resistor, and based on a ratio of M to N.

Abstract: A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins receive timing recovery. The slave freezes its receive timing recovery and locks its transmit clock. The master device transitions its transmit timing to use the recovered receive clock. The slave gradually switches to transmitting using its local clock signal. The method may be used in synchronous Ethernet networks.