Abstract: A device having a digital-to-analog converter (DAC) data generator circuit to perform a function upon an event and generate digital DAC data based on the function and the event, and a DAC circuit to generate an analog waveform signal from the digital DAC data.

Abstract: A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.

Abstract: By arranging both a conductive and non-conductive resistive memory cell in a cross coupled arrangement to facilitate reading a data state the memory cells can have very small differences in their resistance values and still read correctly. This allows both of the memory cells' resistances to change over time and still have enough difference between their resistances to read the desired data state that was programmed. A pair of ReRAM or CBRAM resistive memory devices are configured as a one bit memory cell and used to store a single data bit wherein one of the resistive memory devices is in an ERASE condition and the other resistive memory devices of the pair is in a WRITE condition. Reading the resistance states of the resistive memory device pairs is accomplished without having to use a reference voltage or current since a trip-point is between the conductive states thereof.

Abstract: A Full-Wave Bridge Rectifier (FWBR) input structure for use in an electrical system is delineated comprising, in combination, a pair of input nodes, and a pair of parasitic BJTs coupled in parallel with the pair of input nodes wherein each parasitic BJT has more than one collector. The input structure also includes an inductor and a capacitor connected in parallel across the pair of input nodes; however, one or more inductors, one or more capacitors, a transformer, or the like could be substituted. Each parasitic BJT also has a base coupled to ground through a resistor, a collector tied directly to ground, and another collector tied to a supply voltage VDD through a resistor. The area associated with each emitter is smaller than the area associated with their respective collector coupled to VDD. This arrangement of the parasitic BJTs assists in minimizing their gain in order to diminish their draw on a downstream power supply.