Abstract: A switch which is magnetic pole insensitive is described. The switch includes a Hall effect sensor coupled to a threshold circuit which provides an output signal indicative of the proximity of a magnet, and hence a magnetic field, to the Hall effect sensor regardless of the orientation of the magnet to the Hall effect sensor.

Abstract: A system and method for dynamically disabling partially streamed content may include a server receiving a request from a client. A session may be initiated or continued in response to the request. The server may begin to stream content to the client as a partial fulfillment of the request. While processing the request, the server may determine if the partially streamed content should be disabled. In response to determining that the partially streamed content should be disabled, the server may disable the partially streamed content without terminating the session. Disabling the partially streamed content may involve preventing the client from accessing content referenced by a hyperlink associated with the partially streamed content, or may involve the use of a controller located on the client to disable content streamed to the client.

Abstract: One embodiment of the present invention provides a system that supports concurrent accesses to a skip list that is lock-free, which means that the skip list can be simultaneously accessed by multiple processes without requiring the processes to perform locking operations. During a node deletion operation, the system receives reference to a target node to be deleted from the skip list. The system marks a next pointer in the target node to indicate that the target node is deleted, wherein next pointer contains the address of an immediately following node in the skip list. This marking operation does not destroy the address of the immediately following node, and furthermore, the marking operation is performed atomically and thereby without interference from other processes.

Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).

Abstract: An apparatus, system and method are provided for low-latency start-up of a free-running harmonic oscillator. The exemplary apparatus embodiment comprises a first and second current sources to generate first and second currents; a bias current monitor adapted to detect a magnitude of the second current and to provide a control signal when the magnitude of the second current is equal to or greater than a predetermined magnitude; and a bias controller adapted to switch the first current from the oscillator and to switch the second current to the oscillator in response to the control signal. a reference voltage generator, a comparator, and a bias controller. Exemplary embodiments include reference voltage generator, a comparator, and a bias controller.

Abstract: In one embodiment, a storage subsystem includes a plurality of storage arrays each including a plurality of storage devices. The storage subsystem also includes a plurality of array controllers each coupled to one or more of the plurality of storage arrays. One or more of the arrays corresponds to a failure group. Each array controller may create a storage volume including storage devices belonging to one or more of plurality of storage arrays. In addition, the storage subsystem includes a redundancy controller that may be configured to implement N+K redundancy. The redundancy controller includes configuration functionality that may determine a number of redundant system data blocks to be stored on different storage devices for a given stripe of data that is dependent upon particular values of N and K and upon physical system configuration information.

Abstract: A method for managing a service executing in a zone environment involves receiving a service management request, identifying a collection of requirements required by the service management request, triggering a data collector to collect zone-specific performance attributes from a plurality of zones in the zone environment, identifying at least one zone in the plurality of zones that has zone-specific performance attributes conforming to the collection of requirements, and provisioning the service on the at least one zone based on the service management request.

Abstract: The use of a token-based memory protection technique may provide memory protection in a computer system employing memory virtualization. A token-based memory protection technique may include assigning a unique identifier to an application, process, or thread, and associating the identifier with a block of memory allocated to that application, process, or thread. Subsequent to assigning the identifier, a packet requesting access to that block of memory may include a token to be compared to the identifier. A memory controller may be configured to associate the identifier with the block of memory and to compare the token in the memory request packet to the identifier before granting access. If a second block of memory is subsequently allocated to the application, process, or thread, the identifier may be disassociated with the first block of memory and associated with the second block of memory.

Abstract: A computer system employing memory virtualization may employ a function-based technique for virtual-to-physical address translation. A function-based translation technique may involve replacing a generic trap handler and one or more translation table look-ups with a function to compute a corresponding physical address from a given virtual address. The computer system may be configured to determine a translation function dependent on mappings in one or more translation tables. The computer system may be configured to reorganize a memory, to reorganize one or more translation tables, or to allocate different blocks of memory to an application prior to determining a translation function. Different applications or threads executing on the computer system may employ different translation functions. Different regions of memory may be accessed using different translation functions. Some virtual addresses may be translated using a function while others may be translated using one or more translation table look-ups.

Abstract: An antenna module and a wireless communication device using the same are provided. The antenna module is used for receiving or transmitting at least a wireless signal. The antenna module includes three independent antennas each having a bottom end and a center line. The bottom ends are substantially disposed on the same plane. The bottom ends are substantially arranged in the shape of a regular triangle. Each distance between two neighboring bottom ends is larger than a quarter of the wavelength of the wireless signal. The included angle between each of the center lines and the plane substantially ranges from 50° to 80°.

Abstract: A method for creating a histogram from a plurality of data elements that includes specifying a plurality of internal buckets, wherein each internal bucket of the plurality of internal buckets represent values between an internal minimum value and an internal maximum value, wherein a plurality of differences of the internal minimum value and the internal maximum value of each internal bucket are heterogeneous, populating the plurality of internal buckets with the plurality of data elements based on the internal minimum value and the internal maximum value of each internal bucket to obtain a plurality of populated internal buckets, and outputting the histogram from the plurality of populated internal buckets.

Abstract: Prefetch information is generated for multi-block indirect memory access chains. A method may include selecting a chain of indirect memory accesses of a procedure, the chain comprising a head access that does not depend for its address on another prefetch candidate memory access within the procedure and an indirect access that depends for its address on the head access. The method may further include determining a prefetch-ahead value for the chain, and generating a load operation corresponding to the head access that specifies a target memory address that is dependent upon the prefetch-ahead value and an address of the head access. The method may further include, for a terminal indirect access of the chain, generating a respective prefetch operation that is dependent for its address computation on results of preceding load operations in the same manner as its corresponding terminal indirect access depends upon preceding accesses in the chain.

Abstract: A computer system may employ a first memory virtualization and corresponding virtual-to-physical address translation technique for a first application executing on a processor and a second memory virtualization and corresponding virtual-to-physical address translation technique for a second application executing on the same processor transparent to the first application. Different virtualization and corresponding translation techniques may be employed on a per-thread basis, rather than a per-application basis. Different virtualization and corresponding translation techniques may be employed for accesses to different ranges of virtual or corresponding physical addresses. Different virtualization and corresponding translation techniques may employ different page sizes. A first or second virtualization and corresponding translation technique may include page-based, segment-based, or function-based virtual-to-physical address translation.

Abstract: A computer system may be configured to dynamically select a memory virtualization and corresponding virtual-to-physical address translation technique during execution of an application and to dynamically employ the selected technique in place of a current technique without re-initializing the application. The computer system may be configured to determine that a current address translation technique incurs a high overhead for the application's current workload and may be configured to select a different technique dependent on various performance criteria and/or a user policy. Dynamically employing the selected technique may include reorganizing a memory, reorganizing a translation table, allocating a different block of memory to the application, changing a page or segment size, or moving to or from a page-based, segment-based, or function-based address translation technique.

Abstract: A method for monitoring performance of a mobile device involves intercepting a first monitoring request from a monitoring management host, where the first monitoring request is associated with the mobile device, enabling a monitoring agent associated with the mobile device, establishing a thin listener associated with the monitoring agent, transmitting a second monitoring request, in response to the first monitoring request, to the mobile device, receiving, by the thin listener, data from the mobile device in response to the second monitoring request, analyzing the data received in response to the second monitoring request to obtain an analysis report, and transmitting the analysis report to the monitoring management host, in response to the first monitoring request.

Abstract: A method and system for identifying multi-block indirect memory access chains. A method may include identifying basic blocks between an entry point and an exit point of a procedure, where the procedure includes a control statement governing its execution. It may be determined whether a probability of execution of a given basic block relative to the control statement equals or exceeds a first threshold value. If so, a respective set of one or more chains of indirect memory accesses may be generated, where each chain includes at least a respective head memory access that does not depend for its memory address computation on another memory access within the given basic block. Chains may be joined across basic blocks dependent upon whether the relative execution probabilities of the blocks exceed a threshold value.

Abstract: A method comprises associating a plurality of locks with a data object accessed concurrently by a plurality of threads, where each lock corresponds to a respective partition of the object. The method includes using a first non-blocking transaction (such as a Hardware Transactional-Memory (HTM) transaction) to attempt to complete a programmer-specified transaction. The first non-blocking transaction may access one or more of the locks but may not actually acquire any of the locks. In response to an indication that the first non-blocking transaction failed to complete, the method may include acquiring a set of locks in another non-blocking transaction, where the set of locks corresponds to a set of partitions expected to be accessed in the programmer-specified transaction. If the set of locks is acquired, the method may include performing the memory access operations of the programmer-specified transaction, and releasing the set of locks.

Abstract: A method and system thereof for supporting multiple versions of software, such as software organized as components or objects. In one embodiment, a software component (e.g., a new object) is implemented on a server node. A translator is created on the server node. The translator provides an interface to the new object for an invocation request associated with a different version of the object (e.g., an older version of the object). The new object is referenced by one identifier, and the translator is referenced by another identifier. In essence, the translator provides a form of version transparency.

Abstract: A method for tracing an instrumented program, including triggering a probe in the instrumented program, obtaining an original instruction associated with the probe, loading the original instruction into a scratch space, and executing the original instruction in the scratch space using the thread, wherein executing the original instruction results in placing the instrumented program in a state equivalent to natively executing the original instruction.

Abstract: A method for storing data, that includes receiving a request to store data in a storage pool, queuing the request in an Input/Output (I/O) queue, and issuing the request from the I/O queue upon receipt of a completion interrupt from the storage pool.