Abstract: A network manager automatically sends certain requests in response to selected events generated by network devices. When a device generates an event, the network manager can send stop requests to the device; send different event requests to the device; or send the same event request to the device, but over a different path. The stop request is sent to cut down on network management traffic. The different event requests can be sent to determine why the event was generated by the device in the first place. The same event request can be sent over a different path to determine whether a problem exists with the device itself or with the path to the device.

Abstract: An extraction tool for extracting a module that is detachably connected to a mounting substrate includes a fixed plate that is vertically supported over the module to be extracted. A movable plate is arranged below the fixed plate and a screw is inserted in central openings in each of the fixed and movable plates. A pair of vertically extending side panels are connected at one edge by a hinge to opposite sides of the movable plate. The opposite edge of the respective side panels are used to grip the module to be extracted. A spring biases the side panels inwardly. A rotatable handle is arranged above the fixed plate and is connected to the screw. Lateral rotation of the handle causes a corresponding axial rotation of the screw for moving the movable plate in a vertical direction.

Abstract: An environment is emulated in a host environment. Output generated in the emulated environment is displayed in a window of the host environment. The emulated environment's output is in the form of Postscript commands that map to the entire screen. The host environment emulates the Postscript commands an maps the output to a window. Input associated with the window is retrieved by an event driver running in the host environment. Each instance of input is referred to as an event. Each event is translated into an event of the emulated environment by an event driver. A translated event is stored in shared memory for access by a window server. The event driver notifies the window server that one or more events are queued in shared memory. The window server processes the queued events by, for example, transmitting the event to an application running in the emulated environment.

Abstract: A multiprocessing system having a plurality of processing nodes interconnected by an interconnect network. A home agent is configured to service multiple requests simultaneously. A transaction blocking unit is coupled to a home agent control unit for preventing the servicing of a pending coherent transaction request if another transaction request corresponding to the same coherency unit is already being serviced by the home agent control unit. The transaction blocking unit is further configured such that read-to-share transaction requests in a NUMA mode do not block other read-to-share transaction requests in the NUMA mode.

Abstract: A virtual memory lock is placed upon a region of physical memory within a computer system in response to an I/O request through the use of a range lock. Each range lock represents pages of virtual memory that are present and locked in the physical memory. The range locks are cached in memory and used subsequently to process a lock or unlock request, thus avoiding constant locking or unlocking. Regions of memory that are locked, but have no outstanding I/O operations may still have a range lock existing corresponding to that region. If no range lock exists for an I/O request, the virtual memory lock function is called and a range lock is created for that region. If a range lock exists, its usage counter is incremented. Upon notification of the completion of an I/O operation upon a particular region, the usage counter for the range lock corresponding to that region is decremented, and the range lock continues to exist even if there are no outstanding I/O requests for that region.

Abstract: A method and apparatus for performing reliable data transfer operations over a global computer network are provided. This is accomplished by transmitting data stored on a first computer system connected to the global computer network to a second computer system connected to the global computer network, sending a receipt acknowledgment signal to the first computer system when the data is received on the second computer system, monitoring acknowledgment signals received by the first computer system, and automatically transmitting the data via facsimile if the receipt of the data is not acknowledged within a predetermined time period. In addition, a paging signal is automatically transmitted to a the business partner to indicate that the data has been transferred by facsimile. Unlike prior art techniques, in which data transfers are performed in batch off-line, embodiments of the invention allow for secure data transfer operations to be performed on-line in real-time.

Abstract: A method and apparatus for interfacing between a Segmentation and Reassembly (SAR) circuit and an ATM Cell Interface is disclosed. The interface circuit comprises a transmit FIFO and a receive FIFO. The transmit FIFO transfers data from the System and ATM Layer Core in the SAR circuit to a Cell Interface block, which in turn dispatches the data to the ATM Cell Interface. The receive FIFO transfers data received from the ATM Cell Interface via the Cell Interface block, to the Core. Various interface signals provided between the Core and the transmit FIFO, the transmit FIFO and the Cell Interface block, the Core and the receive FIFO, and the receive FIFO and the Cell Interface block, are used to coordinate data transfer. The interface circuit insulates the Core from the ATM Cell Interface, allowing the Core to operate independently from ATM Cell Interface specifics.

Abstract: A system, method and computer program product comprising a storage manager independent configuration interface translator which requests an opaque listing of the available storage devices from an associated metadisk driver and determines a subset of the listing meeting a preselected search criteria. The resultant opaque listing is then converted to a non-opaque format listing for presentation to a user of the computer system in a desired format such as through a command line or graphical user interface. A notification mechanism is also provided that presents information about storage devices which have in some way changed while in use.

Abstract: A bus line is provided with broadly distributed signal termination by using switched termination logic where the pull up resistance of a driver corresponds to the characteristic impedance of the line and the pull down resistance of the driver corresponds to the number of drivers coupled to the line. Accordingly, signals being transmitted over the bus suffer relatively few reflections thus advantageously producing a shortened signal settling time, thereby increasing the attainable signaling frequency.

Abstract: A method for generating non-blocking multiple-phase clocking system for use with domino-type dynamic logic includes receiving a primary clock signal and generating several delayed phases of the received primary clock signal. The number of clock phases equals the number of dynamic logic gates in the circuit. The method provides a first clock phase to the first dynamic logic gate of the circuit, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives. This adjustment of the clock phases maximizes the logic evaluation speed of the dynamic logic circuit.

Abstract: A computer system which exhibits increased performance for stereo viewing. The computer system includes a display screen, a bus for transferring data, a memory coupled to the bus for storing geometric primitives and left and right view transformation matrices. Furthermore, the computer system includes a processor coupled to the bus, wherein the processor is configured to enable stereo mode and to execute an application for rendering objects on the display screen in the stereo mode. The computer system also includes a graphics accelerator coupled to the bus. The graphics accelerator includes a buffer for storing a received geometric primitive to be rendered in stereo mode, as well as memory for storing the left and right view transformation matrices. The graphics accelerator also includes a transformation unit which is configured to generate a first transformed geometric primitive in response to the received geometric primitive and the left view transformation matrices.

Abstract: An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.

Abstract: The present invention provides a method and system for creating a test script. The invention begins processing when a user requests the automatic creation of a test script. When the user next enters data on a graphical user interface, the data is sent to a display server which manages the input and output on the graphical user interface. The display server creates an event corresponding to the type of input entered on the graphical user interface.In order to examine the context within which the event occurred, the present invention interposes a new version of a routine into the system so that the new routine is called when the GUI program attempts to retrieve the event from the display server buffer. Interposing ensures that the new version of the routine will be invoked before the original version of the routine.

Abstract: In a control block design methodology, control block design proceeds without the inclusion of scan functionality until the functional design specifications are met. After meeting the functional design specifications, a scan insertion tool is executed to automatically insert scan functionality. The insertion is performed in such a manner that the functional cells within the control block are not perturbed. Therefore, functional timing may be minimally affected, if at all. In one embodiment, a scan enable buffer is inserted at the end of each row in the control block. Flops (or other scannable storage devices) within the row are connected to the scan enable line provided by the scan enable buffer within the row. Additionally, flops are connected into a scan chain on a row-by-row basis, minimizing the length of the wires connecting the scan chain. If a particular scan chain wire exceeds a length which will meet scan timing requirements, a scan chain buffer can be inserted as well (e.g. at the end of the row).

Abstract: The present invention provides a phase locked loop (PLL) clock generator for a digital system. The PLL clock generator is capable of an instantaneous transition between a high frequency and a low frequency, corresponding to an active mode and a slow mode, and vice versa The PLL clock generator includes a phase locking circuit, a frequency changer coupled to the output of the phase locking circuit, and a frequency controller coupled to the frequency changer. The frequency changer is capable of instantaneously changing the frequency of a first clock signal received from the phase locking circuit. The frequency controller is responsible for controlling the frequency at the output of the frequency changer. The frequency controller is responsive to a control signal which is used to transition the PLL clock generator from an active mode to a slow mode and vice versa In one embodiment, the phase locking circuit generates the first clock signal in response to a reference clock signal and a feedback clock signal.

Abstract: Arrayed display pixels are coupled such that all row pixels are coupled together by a row conductive element and all column pixels are coupled together by a column conductive element. The row-coupled pixels are driven by first and second row drivers and the column-coupled pixels are driven by first and second column drivers, a total of four drivers in all. The drivers each output time-varying signals of different frequencies. The vertical scan rate is determined by the frequency differential in the signals output by the two row drivers, and the horizontal scan rate frequency is determined by the frequency differential in the signals output by the two column drivers. The absolute frequencies of the four signals are set proportional to the propagation delay of the medium through which the driver signals travel. The invention implements a pixel enabling signal using the beat-frequency difference between two driver source signals that propagate through a pixel string from opposite ends of the string.

Abstract: A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe.

Abstract: A method and apparatus placing blocks of object code by a compiler. The code placement is done optimally, using a "cut set technique" that uses the "max-flow/min-cut" principle. A preferred embodiment of the present invention divides a source program into blocks and generates a control flow graph (cfg) and a data flow graph (dfg) for the blocks. The compiler then identifies the strongly connected components (sccs) of the dfg and recursively breaks down the cycles in each scc to yield a plurality of directed acyclic graphs (dfg-dag's). The compiler then finds the "minimum cut set" in the cfg corresponding to each dfg-dag and moves the code into blocks in accordance with the minimum cut sets. Lastly, the compiler generates object code for the blocks.

Abstract: A frame buffer system is disclosed that employs non overlapping serial enable signals to access pixel data values from sets of pixel buffers contained in each interleave of a multiple interleave frame buffer according to the attribute data in the frame buffer. The frame buffer system provides circuitry for varying the interleave factor between frame buffer accesses and the generation of corresponding video data. The frame buffer system also provides circuitry for expanding double buffered pixel data values into full addressing for color look-up.

Abstract: A method of encoding and storing locations of bounding boxes of drawing primitives to be rendered on a multi-resolution display that includes a plurality of regions of different resolution, at least one of which is subdivided into a plurality of sub-regions. The method includes steps of dividing the viewable area of the multi-resolution display into four quadrants and encoding only selected attributes of each of the plurality of bounding box locations within only one of the four quadrants of the multi-resolution display. The encoded selected attributes are then stored in a number of locations of a memory.