Abstract: A security module for a removable disk drive having a lockable hardware write protect feature for use with docking base. Additional features provided by the invention are an enclosure and electrical connection interface designed to reduce or eliminate radio frequency interference (RFI) and electromagnetic interference (EMI), a removal mechanism that provides for orderly powering down of a disk drive before removal of the security module from a docking base, and a module latching and lock mechanism that provides for positive, lockable securement of the module into a docking base.

Abstract: The system of the present invention provides for the context switching of devices connected through the system's memory management unit and is particularly useful in a multi-tasking computer system in which multiple processes access the same device. In the method and apparatus of the present invention, devices that are connected to the system through the MMU are controlled using the page fault mechanism of the MMU and the page fault handler in each segment. Addresses are allocated in the process address space for each process to provide for the addressing of the devices and device queues connected through the MMU, such that one device or one device queue is mapped into one segment of each process address space that will access the device. The "valid bits" associated with each page in a segment are turned on/off by the process or operating system in order to control the device.

Abstract: An adaptive forward differencing apparatus wherein, when rendering curves, calculated x, y values are increased or decreased in order to create values which correspond to the next pixel of the display CRT, such that curves of substantially one pixel increments are continuously and uniformly generated. The apparatus also provides circuitry for generating coordinates of display elements which approximate an ideal vector and to define curves, vectors or objects within maximum and minimum coordinates of the CRT display. The present invention also provides efficient circuitry for computing the value of 1/w of the homogenous coordinate w.

Abstract: A scan conversion process is performed on a polygon using a single pass technique. The pixels which comprise the edges and vertices of the polygon are first determined from the vertices which define the polygon. The alpha channel comprises either a sub-pixel mask associated with each pixel which indicates the amount and sub-pixel regions of coverage or a single value indicative of the percentage of coverage of a pixel. Furthermore, a z value indicative of the depth of each pixel is maintained. The pixels between the edge pixels of the polygon are then turned on, thereby filling the polygon. The pixels which comprise the polygon are then composited with the background pixels on a per pixel basis. The depth value of each pixel of the polygon (the z value) is used to determine the compositing equations to be used to composite each pixel of the polygon to the background.

Abstract: An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Abstract: An interface which includes a MIDI send terminal having first and second pins for providing an output signal, an RS 232 terminal having first and second pins for receiving a signal from the MIDI send terminal, apparatus for coupling any MIDI output signal to the RS 232 terminal, the apparatus for coupling including apparatus for shifting a base level at which the signals are presented at the MIDI terminal to a base level at which the signals are received at the RS 232 terminal, apparatus for shifting the voltage swing of signals presented at the MIDI terminal to a voltage swing at which the signals are received at the RS 232 terminal, and apparatus for disabling the RS 232 terminal if a device to which the RS 232 terminal is connected would normally respond in an undesirable manner to unexpected data received on the RS 232 terminal.

Abstract: A Tape Automated Bonding (TAB) process prepared multi-chip module (MCM) has semiconductor dice embedded into the substrate of the MCM through its top face. A heatsink, which in a preferred embodiment is a copper slug, is emplaced into the underside of the substrate so that the bottom surfaces of the dice engage the heatsink. A compliant, heat-conducting thermoplastic material is used to secure the dice to the heatsink and to maintain a good heat flow path. According to the present invention, the TAB formed component has beam leads that do not require bending to facilitate assembly. Rather, the beam leads are trimmed to length, leaving straight outer beam leads that, after the die is installed in the substrate, extend parallel to and overlie the top face of the substrate. The beam leads are thus positioned for convenient bonding to signal paths laid out on the top face of the substrate.

Abstract: Improvements in workstations which utilizes virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes directed to the support of alias addresses, i.e., two or more virtual addresses which map to the same physical address in real memory Specifically, alias addresses are created so that their low order address bits are identical, modulo the size of the cache (as a minimum) for user programs which use alias addresses generated by the kernel, or wholely within the kernel. For alias addresses in the operating system, rather than user programs, which cannot be made to match in their low order address bits, their pages are assigned as "Don't Cache" pages in the memory management unit (MMU) employed by workstations which utilize virtual addressing.

Abstract: A pipelined register cache for increasing a computer processor's execution speed by reducing the time required to access register data. A register cache is implemented to keep often-used registers in high-speed storage immediately available to the processor's arithmetic and logic unit (ALU). The register cache is constructed using a number of individual register stages which are connected in series such that the register information contained in each register stage is passed from one register stage to the next in a First-In, First-Out (FIFO) queue arrangement. Each register stage stores a register address tag for identifying the particular primary register being represented in that register stage, and a data value representing the actual register contents. When a register that is not represented in the cache is needed for a calculation, the register information is first loaded from the primary register storage into the first register stage of the register cache.

Abstract: A database system for text files is employed which comprises a compiler which receives as input a description of the source file types or languages and search filter and outputs a tag set definition file and filter file to be used by the browsing mechanism. The tags set definition file is input to the database builder mechanism and is used by the database builder to select and translate the information from the input source file to a database component file. Thus, by providing a description of the source file type, any type of source file in any language can be input to the database system of the present invention to generate a database component file which may be subsequently reviewed and searched by the same browsing mechanism.

Abstract: In a computer graphics system in which information defining graphic images to be presented on an output display is available on a scan line basis for a pair of line segments subtending a portion of the an image to be presented. The information includes the slope of each line segment and the addresses of each line segment on each scan line. A circuit comprising two comparator subportions, each of the comparator subportions being adapted to process information regarding one edge of the portion of the image to be presented and including apparatus for receiving first signals representing values of both of the line segments to be procesed for one scan line. Comparing the signals to determine their relative X positions on the scan line, controlling the determination of the relative X positions and the slope of each line segment, and storing one of the signals compared.

Abstract: A method and apparatus is provided to directly render volumes from volume data whereby the resolution of the volume is not lost and the volume data is completely interactive with geometric data. The volume or portion of the volume to be rendered is aligned to a geometric primitive defined by a reference frame and a mapping function is generated relating the geometric primitive to the volume or volume portion. The mapping function relates each voxel in volume space to an element or point of the primitive. Thus, the volume is displayed as a function of the geometric primitive the volume or volume portion is mapping to. In the preferred embodiment the volume or portion of volume to be rendered is bound by one or more geometric primitives and a mapping is generated relating the geometric primitive, such as a 3-D polgon, to the volume.

Abstract: A balanced tree clock distribution network for an integrated circuit including a branching clock line of layered metal in which each branch of the clock line has equal resistance, apparatus for shielding the clock line on both sides in the same layer of material of the integrated circuit, and apparatus for providing jumpers for crossing the clock line at right angles in a different layer of material of the integrated circuit which jumpers apppear at the same preselected distances along each branch of the clock line.

Abstract: A computer system which includes a central processing unit including a first processing unit that performs basic processing functions and a co-processing unit that performs multiple specialized processing functions concurrently with the first processing unit, an arrangement for detecting the occurrence of a function causing an exception in a result produced by the coprocessing unit, an arrangement for specifying to the first processing unit any exception in a result produced by the coprocessing unit, an arrangement for using the first processing unit to implement any function which causes an exception in a result produced by the co-processing unit, an arrangement for storing the identification of the instruction being handled by the first processing unit when a function causing any exception in a result produced by the co-processing unit occurs, and an arrangement for determing the instruction which produced the exception.

Abstract: A tristate driver circuit including a first output transistor for furnishing a first output voltage at an output terminal in the on condition, the first transistor being susceptible to disablement or degraded operation from back biasing in the presence of voltages above a particular level at the output terminal in the off condition, a second output transistor for furnishing a second output voltage at the output terminal in the on condition, apparatus for biasing the first and second transistors to allow operation thereof in the presence of enable signals and to disable operation in the absence of enable signals, and apparatus for eliminating back biasing of the first transistor in the absence of enable signals.

Abstract: Visible Moire interference is eliminated by alternately shifting the phase of the horizontal sync signal or video signals such that the phase of each video line, and hence the phase of the resulting Moire interference associated with that video line, is also alternately shifted. The phase of the Moire interferences are shifted such that persistence of vision in the human eye averages oppositely phased phosphor intensity variations occurring on alternating scan lines and/or vertical fields. When viewed by a user of the CRT, optical cancellation of the Moire interference patterns results.

Abstract: Apparatus and methods are disclosed which are most advantageously used with a digital computer for detecting the location of multiple cursors in a computer memory having parity bits. In one embodiment of the present invention, the normal parity checking scheme of the computer memory is modified, such that the parity bit is used to detect data locations containing cursor data. Writing new data to the frame buffer is implemented as a read-modified-write cycle. In another embodiment of the present invention, the parity checking of the computer memory is no longer used as such. Instead, the memory controller has a mode that forces the parity bit to one of two states, independent of the contents of the data location. Rather than writing to the frame buffer as a read-modify-write cycle, the memory controller detects the location of the cursor by reading the state of the parity bit while writing the contents of the data location associated with the parity bit.

Abstract: The present invention provides an apparatus and methods to reduce the stray magnetic fields created by the yoke assembly of a cathode ray tube (CRT) visual display device, and emitted from the CRT enclosure. A pair of closed wire loops are brought into contact with the yoke at the point where maximum magnetic radiation is emitted. The magnetic flux emitted from the yoke is coupled into the wire loop pair, inducing therein a current which flows so as to produce an opposing magnetic field to that produced by the CRT yoke. A capacitor in series in the second loop serves to increase the magnitude of the magnetic field produced by the second loop. Measured at a distance, the counteracting magnetic field reduces the total magnetic field emitted from the CRT enclosure.

Abstract: A computer system which has a display memory for storing information to be presented on an output display, and a full screen bitmapped window identification memory for storing information regarding window position on an output display, and uses circuitry for comparing incoming information with information stored in the window identification memory to determine whether the incoming information should appear in a particular window of the output display, and also includes a second full screen bitmapped memory normally utilized for storing information indicative of other than window position on an output display and utilizes circuitry for selectively storing information in the second memory regarding window position on the output display when additional windows are required.

Abstract: A fan assembly with a single fan housing that has at least one fan passage adapted to allow air to flow through the housing. A separate fan subassembly is snapped into a motor housing formed within the passages of the fan housing. The subassembly includes an electric motor that rotates an impeller. The rotation of the impeller creates an airflow through the air passage. Attached to the surface of the housing is a conductor that extends from the motor, to an electrical connector that supplies power to the motor from an external power source. The air passage has rounded entrances and is formed such that the passage is shaped like a venturi tube. The rounded edges reduce the head loss through the passage by an order of magnitude, decreasing the pressure drop across the housing and improving the overall efficiency of the fan.