Patents Assigned to MicroUnity Systems Engineering
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Patent number: 6295599Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.Type: GrantFiled: August 24, 1999Date of Patent: September 25, 2001Assignee: MicroUnity Systems EngineeringInventors: Craig Hansen, John Moussouris
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Patent number: 5274920Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.Type: GrantFiled: January 14, 1992Date of Patent: January 4, 1994Assignee: MicroUnity Systems EngineeringInventor: James A. Matthews
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Patent number: 5263251Abstract: A method of making an ultra compact laminar-flow heat exchanger includes forming microscopic regions along the front side of an elongated ribbon of material and spirally laminating the ribbon into a core wherein the front side abuts the backside of the ribbon, thereby forming enclosed microscopic channels.Type: GrantFiled: January 6, 1993Date of Patent: November 23, 1993Assignee: Microunity Systems EngineeringInventor: James A. Matthews
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Patent number: 5256505Abstract: A mask for transferring square and rectangular features having critical dimensions (CDs) close to the resolution limit of the exposure tool utilized to perform the transference is described. Intensity modulation lines having the opposite transparency as the rectangular feature to be transferred, and a width significantly less than the resolution of the exposure tool, are disposed within the rectangular feature. The intensity modulation lines have the affect of damping intensity levels on the resist layer in the center of the rectangular feature. As a result, the final CD measurement of the rectangular feature is within the CD tolerance of the original designed CD measurement. In addition, since modulation lines are have dimensions well below the resolution limit of the exposure tool, they are not seen in the final rectangular resist pattern.Type: GrantFiled: August 21, 1992Date of Patent: October 26, 1993Assignee: Microunity Systems EngineeringInventors: Jang F. Chen, James A. Matthews
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Patent number: 5112761Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface.Type: GrantFiled: January 10, 1990Date of Patent: May 12, 1992Assignee: MicroUnity Systems EngineeringInventor: James A. Matthews
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Patent number: 5068826Abstract: A non-volatile, static magnetic memory device, whose operation is based on the Hall effect, is disclosed. The device includes a magnetic patch which stores data in the form of a magnetic field, a semiconductor Hall bar and a pair of integrally-formed bipolar transistors used for amplifying and buffering the Hall voltage produced along the Hall bar. Current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases of the bipolar transistors are ohmically coupled to the Hall bar to sense the Hall voltage--the polarity of which is representative of the stored information. A system of current carrying conductors is employed for writing data to individual magnetic patches.Type: GrantFiled: January 11, 1991Date of Patent: November 26, 1991Assignee: MicroUnity Systems EngineeringInventor: James A. Matthews