Abstract: A method for providing scattering bars for optical proximity effect correction on a mask used in a lithographic process. Scattering bar spacing and characteristics are adjusted and varied along with primary feature edge location in order to control CD's of features that are spaced a distance greater than the minimum pitch of a lithographic process but less than a nominal distance for two feature edges having independent scattering bars.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A method and data processing system for transferring data between the system and a memory system using more than one byte ordering convention by incorporating byte order information into instruction codes. The byte order information is coupled to a control unit along with other information characterizing the data transfer operation. In response to the byte order information and the data transfer operation information, the control unit generates a control signal that is coupled to a BPU. The control signal causes the BPU to rearrange the order of bytes in the data being transferred when the byte order information indicates a first byte ordering format. When the byte order information indicates a second byte ordering format, the BPU does not change the order of the bytes in the data being transferred.

Abstract: A floating point system and method employing instructions where instruction have incorporated floating point information. The floating point information indicates whether an exception trap should occur and the type of rounding to be performed upon "inexact" arithmetic results. The floating point information further indicates whether other floating-point exception traps should occur. This information allows dynamic (e.g. instruction-by-instruction) modification of various operating parameters of the CPU without modifying information in status registers using special instructions or modes, thereby increasing overall CPU performance. The technique is also supported by several mechanisms for providing precise floating-point exceptions.

Abstract: A non-blocking load buffer for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates. The memory chip includes a memory device and an interface capable of achieving high bandwidth throughput. The memory device decodes, arbitrates between, and executes memory access commands, and generates memory access responses. The interface includes a data path, and a number of memory controllers. The interface receives and transmits input and output data streams, and the memory controllers control the flow of the input and output data streams within the memory chip. A packet buffer is coupled between the data path and the memory device. The packet buffer provides for temporary storage of memory access commands, response information, and forwarding data.

Abstract: A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced.

Abstract: Methods for improving adhesion between various materials utilized in the fabrication of integrated circuits. A first method relates to improving adhesion between a silicon nitride layer and a silicon dioxide layer. The method includes treating a surface of the silicon dioxide layer with a nitrogen plasma in a reactive ion etching process prior to depositing the silicon nitride film on the surface of the silicon dioxide layer. A second method relates to improving adhesion between a silicon nitride layer and a polyimide layer. The method includes the step of treating a surface of the silicon nitride layer with a oxygen/argon plasma in a reactive ion etching process prior to depositing the polyimide layer film on the surface of the silicon nitride layer. A third method relates to improving adhesion between a photoresist layer and a metal.

Abstract: There is disclosed a photolithography mask and method of making the same that utilizes serifs to increase the correspondence between an actual circuit design and the final circuit pattern on a semiconductor wafer. The mask uses a plurality of serifs having a size determined by a resolution limit of the optical exposure tool used during the fabrication process. The serifs are positioned on the corner regions of the mask such that a portion of surface area for each of the serifs overlaps the corner regions of the mask. The size of the serifs is about one-third the resolution limit of said optical exposure tool. About 33 to about 40 percent of the total surface area of the serifs overlap the corner regions of the mask.

Abstract: A method for synthesizing correction features for an entire mask pattern that initially divides mask pattern data into tiles of data--each tile representing an overlapping section of the original mask pattern. Each of the tiles of data is sequentially processed through correction feature synthesis phases--each phase synthesizing a different type of correction feature. All of the correction features are synthesized for a given tile before synthesizing the correction features for the next tile. Each correction feature synthesis phase formats the data stored in the tile into a representation that provides information needed to synthesize the correction feature for the given phase. Methods for implementing edge bar and serif correction features synthesis phases are also described.

Abstract: The present invention encompasses techniques for reducing digital noise in integrated circuits and circuit assemblies, particularly dense mixed-signal integrated circuits, based upon shaping the noise from the digital circuit and concentrating it in a single, or a small number, of parts of the frequency spectrum. Generally, the presence of noise in the analog circuit is less important at certain frequencies, and therefore the spectral peak or peaks from the digital circuit can be carefully placed to result in little or no interference. As an example, a radio receiver might be designed such that the peaks of the digital noise lie between received channels, outside the band edges of each.

Abstract: A controller for a synchronous DRAM is provided for maximizing throughput of memory requests to the synchronous DRAM. The controller maintains the spacing between the commands to conform with the specifications for the synchronous DRAMs while preventing gaps from occurring in the data slots to the synchronous DRAM. Furthermore, the controller allows memory requests and commands to be issued out of order so that the throughput may be maximized by overlapping required operations which do not specifically involve data transfer. To achieve this maximized throughput, memory requests are tagged for indicating a sending order. Thereafter, the memory requests may be arbitrated when conflicting memory requests are queued and this arbitration process is then decoded for simultaneously updating scheduling constraints. The memory requests may be further qualified based on the scheduling constraints and a command stack of memory request is then developed for modifying update queues.

Abstract: A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

Abstract: A direct digital synthesizer (DDS) for generating a waveform generates a sequence of n-bit phase signals representing phase of the waveform, wherein n is an integer greater than zero. Each n-bit phase signal comprises a phase estimate signal and a phase error signal. The phase estimate signal comprises a most-significant m bits of the n-bit quantity (0 <m<n). The phase-error signal comprises a least-significant n-m bits of the n-bit quantity. The DDS further has a sigma-delta modulator for generating a compensation signal from the phase error signals. The phase estimate signal is added to the compensation signal to produce a compensated phase signal, which may be used to address a look-up table having waveform samples stored in correspondence with look-up table addresses. A digital to analog converter may be coupled to receive waveform samples from the look-up table in order to generate a corresponding analog waveform signal.

Abstract: An apparatus and method for decorrelating pairs of mutually contaminated channels in a multi-channel digital signal including two identical data processing paths and a feedback path. Each pair of mutually contaminated channels consists of a first contaminated channel and a second contaminated channel. Initially, first and second shined signals are generated by shifting the original contaminated signal such that the first shined signal has the first contaminated channel centered at zero frequency and the second shined signal has the second contaminated channel centered at zero frequency. Each of the first and second shifted signals are coupled to one of the two identical signal processing paths. The first path generates an error corruption component corresponding to the first shifted input signal and subtracts this corruption component from the second shifted signal in order to generate a third decorrelated digital signal.