Abstract: An error correction code decoder, including a computational memory array having at least a variable node section, a check node section, and a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on the bit and each cell implementing one node. A controller instructs the computational memory to perform the operations and to write the results of computations on a block of variable nodes into associated set of blocks of check nodes and to write the results of computations on a block of check nodes into associated set of blocks of variable nodes.

Abstract: A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.

Abstract: A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern.

Abstract: An error correction code decoder comprising a computational memory array having at least a variable node section and a check node section, said computational memory array comprising a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on said bit and each cell implementing one node; and a controller to instruct said computational memory to perform said operations and to write the results of computations on a block of variable nodes into its associated set of blocks of check nodes and to write the results of computations on a block of check nodes into its associated set of blocks of variable nodes.