Patents Assigned to Mil Computing, Inc.
  • Patent number: 9690581
    Abstract: A computer processor and corresponding method of operation employs execution logic that includes at least one functional unit and operand storage that stores data that is produced and consumed by the at least one functional unit. The at least one functional unit is configured to execute a deferred operation whose execution produces result data. The execution logic further includes a retire station that is configured to store and retire the result data of the deferred operation in order to store such result data in the operand storage, wherein the retire of such result data occurs at a machine cycle following issue of the deferred operation as controlled by statically-assigned parameter data included in the encoding of the deferred operation.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: June 27, 2017
    Assignee: Mil Computing, Inc.
    Inventors: Roger Rawson Godard, Arthur David Kahlich, Nachum Kanovsky, David Arthur Yost, Sebastien Paul Maurice Mirolo