Abstract: Embodiments of the present disclosure are directed to a photonic implementation of a processor for message generation for digital currency (e.g., bitcoin) transactions. The processor includes an input photonic circuit and a message generation photonic circuit coupled to the input photonic circuit via a first set of optical connections. The input photonic circuit receives input data of a first size and splits the received input data into a plurality of input messages of a second size. The message generation photonic circuit receives the plurality of input messages from the input photonic circuit via the first set of optical connections, and generates a plurality of output messages of the second size based at least in part on the plurality of input messages.

Abstract: Embodiments of the present disclosure are directed to an integrated circuit with photonic bit-corrector circuits. The integrated circuit includes a photonic circuit, a photonic bit-corrector circuit, a photodetector array coupled to the photonic bit-corrector circuit, and an electronic circuit coupled to the photodetector array. The photonic circuit includes a plurality of cascaded photonic gates configured to generate a first photonic output signal for a set of photonic input signals applied to the photonic circuit. The photonic bit-corrector circuit is configured to generate a second photonic output signal for the set of photonic input signals applied to the photonic bit-corrector circuit. The photodetector array is configured to generate an electrical signal based on the second photonic output signal. The electronic circuit is configured to compare the electrical signal with a label signal and output a corrected version of the first photonic output signal based on the comparison.

Abstract: A photonic circuit with at least one nonlinear amplitude thresholder for correcting errors produced by linear photonic logic. One or more photonic input gates of the photonic circuit receive one or more input signals and generate one or more photonic signals based on the one or more photonic input signals. A first set of one or more photonic gates of the photonic circuit generates one or more intermediate photonic signals based on the one or more photonic signals. The at least one nonlinear amplitude thresholder generates at least one photonic thresholding signal based on the one or more intermediate photonic signals, the at least one nonlinear amplitude thresholder operating in a first operating regime, second operating regime, and/or third operating regime. A second set of one or more photonic gates of the photonic circuit generates one or more photonic output signals based on the at least one photonic thresholding signal.

Abstract: A photonic circuit for generating an ultrafast clock for a photonic processor. The photonic circuit includes a beam splitter, a phase shifter, a first photonic combiner coupled to the beam splitter and the phase shifter, and a second photonic combiner coupled to the beam splitter and the first photonic combiner. The beam splitter splits a received photonic seed clock signal into a first photonic seed clock signal and a second photonic seed clock signal. The phase shifter shifts a phase of a received photonic signal to generate a phase-shifted version of the photonic signal. The first photonic combiner combines the second photonic seed clock signal with the phase-shifted version of the photonic signal to generate a first combined photonic signal. The second photonic combiner combines a delayed and attenuated version of the first photonic seed clock signal with the first combined photonic signal to generate a photonic clock signal.

Abstract: Embodiments of the present disclosure are directed to a photonic implementation of a processor for keys update and hash generation for digital currency (e.g., bitcoin) transactions. The processor includes a first photonic circuit and a second photonic circuit coupled to the first photonic circuit via a set of optical connections. The first photonic circuit is configured to generate a plurality of new messages based at least in part on a plurality of input messages. During a plurality of operational cycles, the second photonic circuit is configured to receive, from the first photonic circuit via the set of optical connections, the plurality of new messages, and update a plurality of keys based at least in part on the received plurality of new messages. The second photonic circuit is further configured to generate at least one hash value based on the plurality of keys generated after the plurality of operational cycles.

Abstract: Embodiments of the present disclosure are directed to an integrated circuit with photonic bit-corrector circuits. The integrated circuit includes a photonic circuit, a photonic bit-corrector circuit, a photodetector array coupled to the photonic bit-corrector circuit, and an electronic circuit coupled to the photodetector array. The photonic circuit includes a plurality of cascaded photonic gates configured to generate a first photonic output signal for a set of photonic input signals applied to the photonic circuit. The photonic bit-corrector circuit is configured to generate a second photonic output signal for the set of photonic input signals applied to the photonic bit-corrector circuit. The photodetector array is configured to generate an electrical signal based on the second photonic output signal. The electronic circuit is configured to compare the electrical signal with a label signal and output a corrected version of the first photonic output signal based on the comparison.