Abstract: An automated system for partitioning a set of Boolean logic equations onto one or more devices selected from a plurality of commercially available devices. The system utilizes a processor having a memory containing information on the different architectural types of devices, physical device information on individual devices and user generated design constraints, weighting factors and partitioning directives. Based upon this stored information, the system of the present invention selects all acceptable architectural types of devices wherein at least one of the Boolean logic equations can be placed thereon. For all physical devices associated with the acceptable architectural types only those devices which fall within the selected user constraints are selected. The system then evaluates the weighting factors to order the devices in order of cost value and then fits the equations according to the partitioning directives to the devices.

Abstract: During compiling, a PLD circuit design system inserts nodes in the two level sum-of-product representation of the target circuit at function and procedure boundaries, the carries between bits of arithmetic operators, and the implicit nodes in complicated if statements. The nodes are collapsed providing that the number of unique symbols in the collapsed equations are .ltoreq. than a first predetermined limit, the number of product terms are .ltoreq. a second predetermined limit, and provided the collapsed equations meet constraints depending on whether or not there are inverters or XOR gates available, and whether or not the inverters and XOR gates are fusible. For all registers in the design, equations are generated to fit any possible flip-flop implementation of the register. Both the ON and OFF equations are generated and carried through the entire optimization process so that the DONT CARE information is retained and optimally used in the final equation reduction and device implementation.

Abstract: An automated system for partitioning a set of Boolean logic equations onto one or more devices selected from a plurality of commercially available devices. The system utilizes a processor having a memory containing information on the different architectural types of devices, physical device information on individual devices and user generated design constraints, weighting factors and partitioning directives. Based upon this stored information, the system of the present invention selects all acceptable architectural types of devices wherein at least one of the Boolean logic equations can be placed thereon. For all physical devices associated with the acceptable architectural types only those devices which fall within the selected user constraints are selected. The system then evaluates the weighting factors to order the devices in order of cost value and then fits the equations according to the partitioning directives to the devices.

Abstract: An automated waveform analyzer for designing, on a computer, a logic implementation of an interface circuit connected between a first digital device and one or more other digital devices. The analyzer identifies from the remaining input and output waveforms those waveforms that, when logically combined together, construct the waveform of a selected output waveform in order to provide the proper logic and timing compatibility between the devices.