Abstract: A procedure which is a particular type of software pipelining is provided which increases the efficiency with which code is executed by reducing or eliminating stalls such as by filling delay slots. The process includes moving instructions in a loop from one loop iteration to another. The moving of instructions provides the scheduler with additional independent instructions in a given basic block so the scheduler has greater freedom to move instructions into unfilled delay slots. The procedure includes changing the entry point into the loop, thus effectively moving an instruction from near the top of the loop to near the bottom of the loop, while changing the iteration number of the moved instruction.

Abstract: A redundant array element or signal line is selectively added and an defective array element or signal line is eliminated by the method and apparatus of the present invention. A multiplexor receives an input signal and a neighboring input signal and outputs one of these two input signals in response to a control signal. A fuse is provided in connection with each output line and configured such that if the fuse is unblown, the device selects the same input as was selected by its upstream neighbor. If a fuse if blown, the multiplexor will select the second input and will output a control signal to its downstream neighbor causing the downstream neighbor to also output its second input line and to output a control signal to its downstream neighbor to select the second input line. The substitution of a redundant element or line is achieved by blowing a single fuse and the circuitry adds only a single mux delay to the critical path.

Abstract: A low-noise high-speed output buffer receives digital control signals for varying the switching delay and di/dt of the buffer. For a plurality of output buffers, one buffer is used to determine the digital control signal values for the rest. The switching delay is controlled by referencing the one output buffer's delay to a clock cycle (e.g., 0.75 T or T, where T equals the clock cycle period). The digital control signal values which define the delay with reference to the clock cycle also determine the di/dt for the output buffers. As process or operating conditions vary, the control signal values change to maintain the delay in the prescribed relation to the clock cycle. Accordingly, the absolute di/dt values change. Thus, the output signal is available by the time needed (e.g., 0.75 T), while the di/dt is varied to an optimum setting based on the absolute delay time.

Abstract: A slot determination mechanism wherein a number of bus units establish their positions along the bus and the total number of units on the bus. The units are connected in a bidirectional daisy chain. A one-cycle reset pulse is sent downstream to unit 1 (the upstream unit). Each unit on receiving one or more pulses from upstream sends that many plus one pulses downstream and then sends a one pulse upstream. Each unit then transmits upstream whatever it receives from downstream. The number of pulses received from upstream provide the slot number. The total number of pulses received from upstream and downstream provide the total number of units.

Abstract: A cache-based computer architecture is disclosed in which the address generating unit and the tag comparator are packaged together and separately from the cache RAMs. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and the tag busses.

Abstract: A system for synchronizing the operation of a CPU and coprocessor operating from a common clock signal includes a first voltage controlled delay line connected to receive the clock signal and delay it by a fixed time interval before supplying it to one of the CPU or coprocessor. A second voltage controlled delay line is connected to receive the clock signal and delay it by an adjustable time interval before supplying it to the other of the CPU or coprocessor. The time interval of the second delay line is determined by the potential of a control signal generated from a phase locked loop circuit coupled to the output terminals of the CPU and coprocessor.

Abstract: A solution to the problem in differential buses that the bus state for a given line pair is undefined when no unit is driving either of the bus lines in the pair. The lines in the bus pair are terminated to different voltage levels, thereby establishing a desired default condition when no unit is driving either line. The voltage offset between the two bus lines must be sufficient that differential receivers coupled to the bus when the bus is not driven can respond to the offset. At the same time, the offset must not be so great that a driver attempting to drive the bus pair cannot overcome the offset with enough margin for the receivers.

Abstract: A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.

Abstract: In data processing systems of the type operable to perform floating point computations there is provided a method, and apparatus implementing that method, for predicting, in advance of the floating point computation, whether or not the computation will produce a floating point exception (e.g., overflow, underflow, etc.). The prediction method includes the steps of combining the exponent fields of the operands of the computation in a manner dictated by the type of operation (i.e., add, subtract, multiply, etc.), and comparing that combination, together with an indication of the computation to be performed (e.g., add, substract, multiply, or divide), to obtain an indication of the possibility of the computation ending in a floating point exception.

Abstract: Apparatus is disclosed for buffering writes from a CPU to main memory, in which sequential write requests to the same address are gathered and combined into a single write request. The embodiment described does not permit gathering with the write request in the buffer which is next scheduled for action by the main memory bus controller, nor does it permit gathering with other than the immediately preceding write request. The invention is implemented using a plurality of buffer ranks, each comprising a data rank, an address rank, and a valid rank for indicating which bits or bytes of the data rank contain data to be written to memory.