Abstract: Systems, methods, and an article of manufacture for performing serial concatenated decoding are shown and described. The decoding includes monitoring a measure of the number of corrections made to a plurality data blocks during outer decoding and determining whether applying sub-optimal inner decoding would reduce a computational load experienced by a processor performing the serial concatenated decoding when compared to the computation load experienced by the processor when optimal inner decoding is applied.

Abstract: An interface circuit configured to connect between (a) a broadcast receiver tuner and associated circuitry for the receiving and processing of broadcast radio frequency signals, and (b) a general purpose computer device programmed with software demodulation code configured to engage a general purpose processor in signal demodulation functions, the interface circuit comprising: a data interface comprising a packetisation buffer connected to receive (i) digital signal sample data from a signal path of the tuner and associated circuitry and (ii) indications of control settings which are applied to one or more configurable components during taking of the sample data, said packetisation buffer being operable to construct packets comprising blocks of sample data and header information carrying said control settings indications; a control interface configured to receive control instructions from tuner control code running on the general purpose computer device; and a microcontroller operable to receive the control i

Abstract: Systems, methods, and an article of manufacture for the reduction in process load experienced by a primary processor when executing an application by dynamically reassigning portions of the application to one or more secondary processors are shown and described. A second processing unit is queried for one or more characteristics. One or more performance characteristics of the second processor are measured. A portion of the application can be reassigned to the second processing unit based on the queried characteristics and performance measurements.

Abstract: An interface circuit configured to connect between (a) a broadcast receiver tuner and associated circuitry for the receiving and processing of broadcast radio frequency signals, and (b) a general purpose computer device programmed with software demodulation code configured to engage a general purpose processor in signal demodulation functions, the interface circuit comprising: a data interface comprising a packetisation buffer connected to receive (i) digital signal sample data from a signal path of the tuner and associated circuitry and (ii) indications of control settings which are applied to one or more configurable components during taking of the sample data, said packetisation buffer being operable to construct packets comprising blocks of sample data and header information carrying said control settings indications; a control interface configured to receive control instructions from tuner control code running on the general purpose computer device; and a microcontroller operable to receive the control i

Abstract: A bridge circuit configured for connection between a tuner circuit capable of receiving broadcast analogue frequencies and a general purpose processor capable of demodulating the received broadcast signal, the circuit comprising: a tuner interface capable of receiving at least one signal component in analogue form from tuner circuitry; an analogue to digital converter connected to receive the analogue signal from the tuner interface and convert it to a digital signal for filtering; a digital filter connected to receive and filter the digital signal; an external digital interface; and a microcontroller arranged to receive control information via said external digital interface, wherein one or more or the analogue to digital converter and the digital filter is provided with a controllably variable clock input.