Abstract: A method for managing information of FRUs is implemented by a BMC that connects to multiple electronic devices and a user-end device. The method includes: sending a query to each electronic device requesting information datasets therefrom, each of which includes header information; for each information dataset, when determining that the electronic device corresponding to the information dataset is an FRU based on the header information, generating an identification code that corresponds to the information dataset, and storing the information dataset and the identification code; when receiving, from the user-end device, an OEM command requesting for all identification codes, sending the identification codes to the user-end device; and when receiving a command set that includes one of the identification codes stored in the BMC, sending the information dataset that corresponds to the one of the identification codes to the user-end device.

Abstract: A multi-master control circuit includes signal switch, D-type flip-flop, and multiplexer. The signal switch outputs switching signals based on a first control signal generated by a first processor or a second control signal generated by a second processor. The D-type flip-flop includes clock input, signal input, signal output, and inverted signal output. The clock input is coupled to the signal switch to receive the switching signals, and the inverted signal output is coupled to the signal input. Upon triggering by the switching signals, the signal output of the D-type flip-flop generates a selection signal. The multiplexer receives a first access signal generated by the first processor and a second access signal generated by the second processor. The multiplexer is coupled to the signal output of the D-type flip-flop to receive the selection signal and output either the first access signal or the second access signal based on the selection signal.

Abstract: A firmware verification method for a management system including a control circuit, a first protection circuit, a second protection circuit, a first memory and a second memory. The first memory includes first firmware including first secondary boot firmware and first primary boot firmware. The second memory includes second firmware including second secondary boot firmware and second primary boot firmware.

Abstract: A multi-node server with power scaling includes a power supply unit and a plurality of node motherboards. Each of the node motherboards includes a power switch unit, a protection module, and a processing module. The power switch unit is configured to generate an output voltage based on an operating current received from the power supply unit. The protection module includes a comparator unit and a logic unit. The comparator unit is configured to generate a first logic signal and a second logic signal based on the output voltage, a first reference voltage and a second reference voltage. The logic unit is configured to perform a logical operation based on the first logic signal, the second logic signal, and a setting signal in order to generate a power control signal that switches between a power suppressing logic level and a non-power suppressing logic level.

Abstract: A method for automatically requesting network management data is implemented using a system including a network management server and a client device connected to the network management server. The method includes: after being powered on, by the client device automatically generating and transmitting a request packet to the network management server, the request packet including both a first parameter field and a request for an IP address, the first parameter field being for requesting parts of network management data; in response to receipt of the request packet, by the network management server, generating and transmitting a replying packet to the client device, the replying packet including a second parameter field, the content of the second parameter field containing the parts of the network management data, wherein the second parameter field indicates a latest version number of firmware for the client device.

Abstract: A multi-node server includes a plurality of nodes. Each of the nodes includes a power supply, a transmission circuit, and a control circuit. The power supply is configured to provide a power source. The transmission circuit is configured to transmit the power source and a power status signal to the transmission circuit of the two adjacent nodes, and receive the power source and the power status signal of the two adjacent nodes. The control circuit is configured to control the transmission circuit and the power supply to transmit the power source and the power status signal to the transmission circuit of the two adjacent nodes. The transmission circuit of each of the nodes are connected in series as a ring circuit. The number of the nodes is N, the power of the power supply is Ps, the total power budget of the multi-node server is Pb, and Ps=Pb/(N?1).

Abstract: A server system includes a management circuit and a processing circuit. The management circuit includes a first control circuit, a second control circuit and a first memory. The first control circuit includes a storage unit and firmware. The storage unit is configured to store a first list. The firmware includes a plurality of daemons. The second control circuit is coupled to the first control circuit. The first memory is coupled to the first control circuit. The first memory is configured to store a first verification value. The processing circuit is coupled to the management circuit. The processing circuit includes a second memory and a power control circuit. The second memory is coupled to the first control circuit. The second memory is configured to store a second verification value and processing circuit identification information. The power control circuit is coupled to the second control circuit and a power supply.

Abstract: A multi-master control circuit includes signal switch, D-type flip-flop, and multiplexer. The signal switch outputs switching signals based on a first control signal generated by a first processor or a second control signal generated by a second processor. The D-type flip-flop includes clock input, signal input, signal output, and inverted signal output. The clock input is coupled to the signal switch to receive the switching signals, and the inverted signal output is coupled to the signal input. Upon triggering by the switching signals, the signal output of the D-type flip-flop generates a selection signal. The multiplexer receives a first access signal generated by the first processor and a second access signal generated by the second processor. The multiplexer is coupled to the signal output of the D-type flip-flop to receive the selection signal and output either the first access signal or the second access signal based on the selection signal.

Abstract: A method for backing up a configuration file of a computer device is implemented by a baseboard management controller, and includes steps of: mounting a first partition, a second partition and a third partition of a flash memory storage device of the computer device; storing a copy of the configuration file in at least one of the first partition, the second partition and the third partition that has been mounted successfully as a backup; running an operating system stored in the flash memory storage device; and neither reading nor writing to the third partition while running the OS.

Abstract: A fixing frame for a computer apparatus includes a frame body defining a plurality of receiving sub-spaces each configured for receiving a first or second electronic device. One side wall of the frame body is provided with protruding portions each defining a mounting groove and having an elongated sliding slot formed in a groove base wall of the mounting groove, and spaced-apart first and second positioning portions. A plurality of stop modules are respectively disposed in the protruding portions. Each stop module includes a slider having a stop plate portion, and an elastic positioning member having a movable portion. The stop plate portion is configured for stopping the first or second electronic device when the movable portion is engaged to the first or second positioning portion.

Abstract: A method of booting a computer is provided. The computer includes a processing unit, and a baseboard controlling unit storing a prioritized option of boot device and a prioritized type of boot hard disk. The method includes steps of: the processing unit sending a first query about the prioritized option of boot device to the baseboard controlling unit; in response to receiving the prioritized option of boot device from the baseboard controlling unit, when the processing unit determines that the prioritized option of boot device is hard disk, the processing unit sending a second query about the prioritized type of boot hard disk to the baseboard controlling unit; and in response to receiving the prioritized type of boot hard disk from the baseboard controlling unit, the processing unit booting the computer from a hard disk that corresponds to the prioritized type of boot hard disk.

Abstract: A firmware verification method for a management system including a control circuit, a first protection circuit, a second protection circuit, a first memory and a second memory. The first memory includes first firmware including first secondary boot firmware and first primary boot firmware. The second memory includes second firmware including second secondary boot firmware and second primary boot firmware.

Abstract: A server system includes a first control circuit and a second control circuit. The first control circuit includes a first controller, a second controller, a first input/output circuit, and a second input/output circuit. The first input/output circuit is coupled to the first controller. The second input/output circuit is coupled to the second controller and the first input/output circuit. The second controller is configured to transmit a debug log of the first control circuit to the second input/output circuit. The second input/output circuit is configured to transmit the debug log of the first control circuit to the first input/output circuit. The second control circuit is coupled between the first input/output circuit and the second input/output circuit. The second control circuit is configured to selectively control data to be transmitted from the first input/output circuit to the second input/output circuit.

Abstract: A method of recording error event is implemented by a processing module in connection to a BMC, the method includes steps of: when a correctable error has occurred in a hardware module, obtaining a current error frequency related to occurrence of the correctable error, and generating error event data related to the correctable error; when the current error frequency is greater than a first threshold, adjusting a notification upper limit corresponding to the hardware module from a default value to an alternative value; increasing an error count value by one; when the error count value has not reached the notification upper limit, returning to the step of obtaining the current error frequency; and when the error count value has reached the notification upper limit, sending the error event data to the BMC, setting the error count value to zero, and returning to the step of obtaining the current error frequency.

Abstract: A method is to be implemented by a baseboard management controller included in a computer system, and includes: upon receiving a power-on signal, loading one of a default basic input/output system (BIOS) image and a golden BIOS image stored in the computer system, and simultaneously starting first and second timers; determining whether a power-on self-test (POST) code is received via a first specific interface before the first timer times out; executing a BIOS recovery procedure when no POST code is received via the first specific interface before the first timer times out; determining whether a signal received via a second specific interface has one of a rising edge and a falling edge before the second timer times out; and executing the BIOS recovery procedure when the signal received via the second specific interface has neither the rising edge nor the falling edge before the second timer times out.

Abstract: A method for managing information of FRUs is implemented by a BMC that connects to multiple electronic devices and a user-end device. The method includes: sending a query to each electronic device requesting information datasets therefrom, each of which includes header information; for each information dataset, when determining that the electronic device corresponding to the information dataset is an FRU based on the header information, generating an identification code that corresponds to the information dataset, and storing the information dataset and the identification code; when receiving, from the user-end device, an OEM command requesting for all identification codes, sending the identification codes to the user-end device; and when receiving a command set that includes one of the identification codes stored in the BMC, sending the information dataset that corresponds to the one of the identification codes to the user-end device.

Abstract: A touchscreen calibration method and a readable storage media are provided. The method includes: A processor accesses a system administrative events database, which is configured to record a pointer error event; and the processor executes a calibration process when the processor determines the pointer error event does exist. The calibration process includes: disabling a plurality of touchscreens; re-enabling the plurality of touchscreens after a preset time period; loading an apparatus registry file after the plurality of touchscreens are restarted; and establishing connections between the processor and the plurality of touchscreens based on the apparatus registry file.

Abstract: A synchronizing system includes a phase-locked loop (PLL), first and second network controllers (NCs), a retimer and a processor. The PLL receives a local oscillator (LO) signal, generates and outputs a clock signal and a synchronizing signal. The retimer and the first and second NCs operate according to the clock signal. The first/second NC generates a first/second clock-event signal based on the synchronizing signal. The processor generates a first/second Precision Time Protocol (PTP) signal based on the first/second clock-event signal, and transmits the first/second PTP signal to the first/second NC. The second NC delivers the second PTP signal to first transceivers. The retimer performs retiming on the first PTP signal, and delivers the same to second transceivers. In a master mode, the PLL unit generates the synchronizing signal based on the LO signal and a reference time signal received from a global navigation satellite system (GNSS).

Abstract: A server and an updating method for a MAC address are provided in the present application. The server includes: a network chipset having a preset first MAC address; a first non-volatile memory storing the first MAC address of the network chipset; a second non-volatile memory storing a first BIOS code data; a central processing unit coupled to the network chipset and the second non-volatile memory; and a baseboard management controller coupled to the central processing unit, the first non-volatile memory, and the second non-volatile memory. The baseboard management controller reads the first non-volatile memory to obtain the first MAC address and stores a second BIOS code data including the first MAC address to the second non-volatile memory, causing the first BIOS code data to be overwritten by the second BIOS code data.

Abstract: A multi-node server includes a plurality of nodes. Each of the nodes includes a power supply, a transmission circuit, and a control circuit. The power supply is configured to provide a power source. The transmission circuit is configured to transmit the power source and a power status signal to the transmission circuit of the two adjacent nodes, and receive the power source and the power status signal of the two adjacent nodes. The control circuit is configured to control the transmission circuit and the power supply to transmit the power source and the power status signal to the transmission circuit of the two adjacent nodes. The transmission circuit of each of the nodes are connected in series as a ring circuit. The number of the nodes is N, the power of the power supply is Ps, the total power budget of the multi-node server is Pb, and Ps=Pb/(N?1).