Abstract: A tone detector comprising a circuit for detecting multi-frequency dialing (DTMF) signals applied to an input terminal and for generating a "DTMF present" indicating signal, and a circuit for detecting the presence of supervisory signals applied to the input terminal and for generating a "supervisory signal present" indicating signal. The dialing tones are converted to digital value signals and are preferably stored in a shift register. The digital value signals and the supervisory signals are applied in serial form to an output terminal. The "DTMF present" indicating signal is applied to a "DTMF present" terminal. Accordingly the presence of the "DTMF present" indicating signal can be monitored and thereby indicate whether the signal present on the output terminal is a digital value signal or a supervisory tone present indicating signal.

Abstract: A photosensitive diode element and method of manufacture. The diode element is comprised of a first layer of n-type hydrogenated amorphous-silicon forming a cathode, and a second layer of p+ type material forming an anode, the second layer overlying the first layer and being transparent to optical energy. As a result of using hydrogenated amorphous-silicon, the phtosensitive diode element according to the present invention has characteristics of high photoconductivity, controllably variable optical gap, and thin film structure. A photosensitive diode array formed from the subject diode elements is easily fabricated, employs straightforward circuitry for addressing each diode element, and is characterized by low crosstalk between elements, maximized optical sensitivity and broad dynamic range.

Abstract: A digital signal processing system for use as a digital service unit within a communication switching system, comprised of a plurality of digital signal processing (DSP) modules for connection via a dedicated programmable digital switch forming part of a circuit switch matrix, to one or more input/output ports such as line circuits, trunk circuits, etc., under control of a main system controller, such as a microprocessor. Applications programs for implementing predetermined service features, are downloaded from the main controller via the circuit switch matrix and digital switch, to one or more of the digital signal processing modules for storage within internal memories thereof. The main controller dynamically allocates circuit switch and message channels of the programmable digital switch in accordance with the signal bandwidth and computation power required to implement the predetermined service features.

Abstract: A method of depositing P-type material on one or more semiconductor substrate wafers in a MOSFET fabrication process, utilizing boron disks. The boron disks are passivated by exposing them to nitrogen gas within a reaction chamber, and then subsequently oxidized by flowing gaseous oxygen thereover. P-type material is diffused from the boron disks onto the surface of the wafers by flowing nitrogen gas over the disks and wafers within the reaction chamber, and subsequently flowing a mixture of nitrogen and oxygen gas over the disks and wafers at a predetermined temperature and flow rate, and for a predetermined length of time. The wafers produced according to the method of the present invention are characterized by high yield, few surface or near-surface defects, and uniform P+ sheet resistance. The method is substantially less expensive to implement than prior art ion implantation techniques for fabricating MOS devices.

Abstract: Apparatus and method for synchronizing a local clock signal with a remote clock signal. The local clock signal is divided by a digital counter for generating a phase increment signal. The phase increment signal and the remote clock signal are applied to a further digital counter for counting the number of phase increment signal cycles received during a predetermined number of cycles of the received remote clock signal and generating a count value in response thereto. A microprocessor performs a table look-up for retrieving a predetermined digital correction value using an address characterized by the count value. The correction value is applied to a digital-to-analog converter for generating an analog control voltage in response thereto. The analog control voltage is applied to a master voltage control oscillator for generating the local oscillator signal such that the local oscillator signal frequency is adjusted to be synchronized with the remote clock signal in both phase and frequency.

Abstract: A phase locked loop for synchronizing a local digital signal with an incoming data signal is described. Parallel phase and frequency detectors compare the local and incoming signals and generate control pulse signals for controlling the frequency of a voltage controlled oscillator which generates the local digital signal. Logic circuitry is included in both the phase and frequency detectors for adjusting the generated control pulse signals in the event of detection of elongated pulse widths of the incoming data signal, indicating one of either an absence of incoming data signal or a bipolar violation in the event the data signals are ASI encoded. The phase locked loop is characterized by quick pull-in time, large pull-in frequency range, accurate clocking and low cost.

Abstract: A compensation circuit for use with an integrating amplifier having an integrating capacitor connected between an input and output thereof. The integrating amplifier monitors an input signal and generates an integrated output signal in response thereto. The compensation circuit detects sudden variations in the input signal and in response momentarily discharge the integrating capacitor, thereby increasing responsiveness of the integrating amplifier in the event of sudden input signal variations.

Abstract: A frequency doubler for receiving an input clock signal and generating an output signal at twice the input signal frequency and having fifty percent duty cycle. The input signal is received by a tapped delay line and transmitted from a predetermined tap thereof to a first input of an EXCLUSIVE OR gate. The second input of the EXCLUSIVE OR gate receives the undelayed input clock signal and generates the output clock signal in response to performing an EXCLUSIVE OR operation on the delayed and undelayed signals. The duty cycle of the output signal is monitored via a comparator in combination with logic circuitry. The output of the comparator is connected to the up/down input of a digital counter which is clocked once for each cycle of the input signal, and generates a digital count value in response thereto. In the event that the monitored duty cycle is less than fifty percent, the comparator generates an up count signal for incrementing the digital counter.

Abstract: A communication switching system for routing digital voice and data signals and message signals between a plurality of peripheral circuits disposed in one or more peripheral subsystems and a main controller. Each peripheral subsystem is comprised of a peripheral switch matrix controlled by a peripheral control processor for switching the voice and data signals between predetermined peripheral circuits and the circuit switch matrix. The voice, data and message signals are transmitted through a circuit switch matrix of the main controller on predetermined time slot channels. The message signals are transmitted via communication controllers associated with the main controller and each of the peripheral subsystems according to a bit oriented data link protocol. The message signals are transmitted asynchronously during a predetermined one or more dynamically allocated time slot channels of the circuit switch matrix. The data link protocol guarantees error-free transmission of a plurality of message signals.

Abstract: An overcurrent shut down circuit for use in a switching regulator power supply comprised of circuitry for detecting the average current of a pulse width modulated input signal, comparing the average current with a predetermined threshold level and reducing the duty cycle of the pulse width modulated signal to zero thereby shutting off the power supply, in the event the detected current exceeds the threshold level, indicating excess current being drawn from an output circuit of the supply. Time delay circuitry is provided for resetting the shut down circuit and restoring the regulator to normal operation after a predetermined amount of time as elapsed subsequent to the power supply being shut down. The overcurrent shut down circuit provides for recovery from CMOS latch-up and other excess current drawing fault conditions without requiring that the power supply be manually turned off. The circuit is of straightforward and inexpensive design and occupies very little circuit board area.

Abstract: A symmetric finite impulse response filter for receiving a digital input signal and generates a filtered analog output signal for application to a balanced line, such as a tip and ring lead pair. Logic levels of predetermined symmetrical bit pairs of the digital input signal are detected and in response, predetermined corresponding capacitors are selectively switched between bias and reference voltages, thereby charging predetermined voltages proportional to the capacitances of the capacitors. The predetermined voltages are summed in an operational amplifier which, in response produces a filtered analog output signal. Individual capacitors are utilized for realizing each pair of symmetrical coefficients of the filter transfer function, resulting in considerable economy of size. A switched capacitor implementation results in high speed performance, simple design and low cost.

Abstract: A circuit for switching one of two impedance networks to a line carrying AC signals comprising a unity gain amplifier having differential inputs connected across the first one of the impedance networks, and one of the differential inputs and an output connected across the second one of the impedance networks, and a microprocessor control terminal connected to the other of the differential inputs for applying one of either a high impedance or AC ground thereto. The circuit is small, inexpensive, requires no electromechanical parts, and takes up very little circuit board area.

Abstract: A circuit for companding digital signals, incorporating a bidirectional barrel shifter in the form of an array of transmission gate cells for shifting step bits of a compressed PCM signal a predetermined number of locations to the left in response to the magnitude of chord bits thereof. The shifted bits are applied to a linear digital signal bus in the form of an expanded linear representation of the PCM signal. Linear digital signals appearing on the linear bus are compressed via shifting to the right through the barrel shifter and are applied therefrom to a PCM signal bus. The companding circuit is inexpensive, can accommodate both A-law and .mu.-law PCM protocols, is fully static and operates at high speed.

Abstract: A constant current line circuit for connection to balanced tip and ring leads of a telephone line and unbalanced transmit and receive leads of a PABX. A differential amplifier receives and applies incoming audio signals carried by the tip and ring leads to the unbalanced transmit lead, and detects D.C. loop current flowing through the tip and ring leads and generates a D.C. signal in response thereto. A voltage controlled feed current supply, connected in a circuit to the differential amplifier, generates a constant current D.C. voltage to the tip and ring leads in response to receiving the D.C. signal, and an integrator circuit is connected in a feedback path from the output of the differential amplifier to a voltage control input of the supply, for filtering audio signals received by the differential amplifier and regulating the generated D.C. signal to a quiescent value of approximately zero volts. The line circuit provides simultaneous bidirectional signal translation and constant D.C.

Abstract: An expandable moulded cabinet for housing printed circuit boards, which is modular and uses only two kinds of parts. Instead of printed circuit board retainers and a backplane being fastened to a cabinet frame, which would require careful attention to tolerances, the retainers are held by the cabinet in approximately correct positions, and the backplane is supported by and is fixed directly to the retainers alone, and not the cabinet. Thus the only precision tolerances required are to the locations on the backplane where the printed circuit board retainers are supported. An inexpensive and versatile cabinet results.

Abstract: A digital progess tone detector, for connection to a telephone line and a PABX, comprising circuitry for generating one or more reference tones having user definable frequencies and performing single frequency discrete Fourier transforms on one or more signals received from the telephone line at the defined frequencies, and providing an output signal to the PABX in response thereto. The output signal provides an indication of whether or not a predetermined one or more progress tone frequencies have been detected in the received signals. Because the generated reference tone frequencies are user definable, the present invention can be easily adapted for use in various foreign countries having different progress tone frequency requirements. A preferred embodiment of the invention is implemented on a single microcomputer chip in conjunction with peripherals (such as codecs, crosspoint switches, etc.).